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soc/intel/alderlake: Include ADL-N ID 5 0x4618 

This patch adds support for using ADL N 4-core MCH ID 0x4618.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3e4855ce93666c54ab35def9b58e4b13bc9a8672
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This commit is contained in:
Sean Rhodes 2024-02-13 20:44:52 +00:00 committed by Felix Held
parent ccd18d1bb4
commit 00b81adfed
6 changed files with 7 additions and 0 deletions
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1
src/mainboard/intel/adlrvp/ramstage.c
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@ -25,6 +25,7 @@ const struct cpu_power_limits limits[] = {
{ PCI_DID_INTEL_ADL_N_ID_2, 6, 3000, 6000, 25000, 25000, 78000 },
{ PCI_DID_INTEL_ADL_N_ID_3, 6, 3000, 6000, 25000, 25000, 78000 },
{ PCI_DID_INTEL_ADL_N_ID_4, 6, 3000, 6000, 25000, 25000, 78000 },
{ PCI_DID_INTEL_ADL_N_ID_5, 6, 3000, 6000, 25000, 25000, 78000 },
};
WEAK_DEV_PTR(dptf_policy);

1
src/soc/intel/alderlake/bootblock/report_platform.c
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@ -61,6 +61,7 @@ static struct {
{ PCI_DID_INTEL_ADL_N_ID_2, "Alderlake-N" },
{ PCI_DID_INTEL_ADL_N_ID_3, "Alderlake-N" },
{ PCI_DID_INTEL_ADL_N_ID_4, "Alderlake-N" },
{ PCI_DID_INTEL_ADL_N_ID_5, "Alderlake-N" },
{ PCI_DID_INTEL_ADL_S_ID_1, "Alderlake-S (8+8)" },
{ PCI_DID_INTEL_ADL_S_ID_2, "Alderlake-S" },
{ PCI_DID_INTEL_ADL_S_ID_3, "Alderlake-S (8+4)" },

1
src/soc/intel/alderlake/chip.h
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@ -153,6 +153,7 @@ static const struct {
{ PCI_DID_INTEL_ADL_N_ID_2, ADL_N_041_6W_CORE, TDP_6W },
{ PCI_DID_INTEL_ADL_N_ID_3, ADL_N_041_6W_CORE, TDP_6W },
{ PCI_DID_INTEL_ADL_N_ID_4, ADL_N_021_6W_CORE, TDP_6W },
{ PCI_DID_INTEL_ADL_N_ID_5, ADL_N_041_6W_CORE, TDP_6W },
{ PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_35W_CORE, TDP_35W },
{ PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_65W_CORE, TDP_65W },
{ PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_125W_CORE, TDP_125W },

1
src/soc/intel/alderlake/cpu.c
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@ -240,6 +240,7 @@ enum adl_cpu_type get_adl_cpu_type(void)
PCI_DID_INTEL_ADL_N_ID_2,
PCI_DID_INTEL_ADL_N_ID_3,
PCI_DID_INTEL_ADL_N_ID_4,
PCI_DID_INTEL_ADL_N_ID_5,
};
const uint16_t rpl_hx_mch_ids[] = {

1
src/soc/intel/alderlake/fsp_params.c
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@ -539,6 +539,7 @@ static uint16_t get_vccin_aux_imon_iccmax(void)
case PCI_DID_INTEL_ADL_N_ID_2:
case PCI_DID_INTEL_ADL_N_ID_3:
case PCI_DID_INTEL_ADL_N_ID_4:
case PCI_DID_INTEL_ADL_N_ID_5:
return ICC_MAX_ID_ADL_N_MA;
case PCI_DID_INTEL_ADL_S_ID_1:
case PCI_DID_INTEL_ADL_S_ID_3:

2
src/soc/intel/alderlake/vr_config.c
View File

@ -127,6 +127,7 @@ static const struct vr_lookup vr_config_ll[] = {
{ PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
{ PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
{ PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
{ PCI_DID_INTEL_ADL_N_ID_5, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
{ PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
{ PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
@ -187,6 +188,7 @@ static const struct vr_lookup vr_config_icc[] = {
{ PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_ICC(37, 29) },
{ PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_ICC(37, 26) },
{ PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_ICC(27, 23) },
{ PCI_DID_INTEL_ADL_N_ID_5, 6, VR_CFG_ALL_DOMAINS_ICC(37, 29) },
{ PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) },
{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_ICC(102, 55) },
{ PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) },