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cpu/intel/model_2065x: Drop unused c-state code 

None of the mainboards have the magic SpeedStep device, so the C-state
generation function bails out without doing anything. Moreover, this
code is broken and was copied from Sandy Bridge. Thus, drop it.

Change-Id: I580157ee33c599af5fc48b06eeb39cb32c9831ec
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons 2021-01-21 22:05:34 +01:00
parent ae4eba9be5
commit 00d66603db
3 changed files with 1 additions and 158 deletions
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73
src/cpu/intel/model_2065x/acpi.c
View File

@ -28,80 +28,9 @@ static int get_cores_per_package(void)
return cores;
}
static void generate_cstate_entries(acpi_cstate_t *cstates,
int c1, int c2, int c3)
{
int cstate_count = 0;
/* Count number of active C-states */
if (c1 > 0)
++cstate_count;
if (c2 > 0)
++cstate_count;
if (c3 > 0)
++cstate_count;
if (!cstate_count)
return;
acpigen_write_package(cstate_count + 1);
acpigen_write_byte(cstate_count);
/* Add an entry if the level is enabled */
if (c1 > 0) {
cstates[c1].ctype = 1;
acpigen_write_CST_package_entry(&cstates[c1]);
}
if (c2 > 0) {
cstates[c2].ctype = 2;
acpigen_write_CST_package_entry(&cstates[c2]);
}
if (c3 > 0) {
cstates[c3].ctype = 3;
acpigen_write_CST_package_entry(&cstates[c3]);
}
acpigen_pop_len();
}
static void generate_C_state_entries(void)
{
struct cpu_info *info;
struct cpu_driver *cpu;
struct device *lapic;
struct cpu_intel_model_2065x_config *conf = NULL;
/* Find the SpeedStep CPU in the device tree using magic APIC ID */
lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
if (!lapic)
return;
conf = lapic->chip_info;
if (!conf)
return;
/* Find CPU map of supported C-states */
info = cpu_info();
if (!info)
return;
cpu = find_cpu_driver(info->cpu);
if (!cpu || !cpu->cstates)
return;
acpigen_write_method("_CST", 0);
/* If running on AC power */
acpigen_emit_byte(0xa0); /* IfOp */
acpigen_write_len_f(); /* PkgLength */
acpigen_emit_namestring("PWRS");
acpigen_emit_byte(0xa4); /* ReturnOp */
generate_cstate_entries(cpu->cstates, conf->c1_acpower,
conf->c2_acpower, conf->c3_acpower);
acpigen_pop_len();
/* Else on battery power */
acpigen_emit_byte(0xa4); /* ReturnOp */
generate_cstate_entries(cpu->cstates, conf->c1_battery,
conf->c2_battery, conf->c3_battery);
acpigen_pop_len();
/* TODO */
}
static acpi_tstate_t tss_table_fine[] = {

8
src/cpu/intel/model_2065x/chip.h
View File

@ -4,13 +4,5 @@
#define SPEEDSTEP_APIC_MAGIC 0xACAC
struct cpu_intel_model_2065x_config {
int c1_battery; /* ACPI C1 on Battery Power */
int c2_battery; /* ACPI C2 on Battery Power */
int c3_battery; /* ACPI C3 on Battery Power */
int c1_acpower; /* ACPI C1 on AC Power */
int c2_acpower; /* ACPI C2 on AC Power */
int c3_acpower; /* ACPI C3 on AC Power */
int tcc_offset; /* TCC Activation Offset */
};

78
src/cpu/intel/model_2065x/model_2065x_init.c
View File

@ -20,83 +20,6 @@
#include <cpu/intel/common/common.h>
#include <smp/node.h>
/*
* List of supported C-states in this processor
*
* Latencies are typical worst-case package exit time in uS
* taken from the SandyBridge BIOS specification.
*/
static acpi_cstate_t cstate_map[] = {
{ /* 0: C0 */
}, { /* 1: C1 */
.latency = 1,
.power = 1000,
.resource = {
.addrl = 0x00, /* MWAIT State 0 */
.space_id = ACPI_ADDRESS_SPACE_FIXED,
.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD,
}
},
{ /* 2: C1E */
.latency = 1,
.power = 1000,
.resource = {
.addrl = 0x01, /* MWAIT State 0 Sub-state 1 */
.space_id = ACPI_ADDRESS_SPACE_FIXED,
.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD,
}
},
{ /* 3: C3 */
.latency = 63,
.power = 500,
.resource = {
.addrl = 0x10, /* MWAIT State 1 */
.space_id = ACPI_ADDRESS_SPACE_FIXED,
.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD,
}
},
{ /* 4: C6 */
.latency = 87,
.power = 350,
.resource = {
.addrl = 0x20, /* MWAIT State 2 */
.space_id = ACPI_ADDRESS_SPACE_FIXED,
.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD,
}
},
{ /* 5: C7 */
.latency = 90,
.power = 200,
.resource = {
.addrl = 0x30, /* MWAIT State 3 */
.space_id = ACPI_ADDRESS_SPACE_FIXED,
.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD,
}
},
{ /* 6: C7S */
.latency = 90,
.power = 200,
.resource = {
.addrl = 0x31, /* MWAIT State 3 Sub-state 1 */
.space_id = ACPI_ADDRESS_SPACE_FIXED,
.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD,
}
},
{ 0 }
};
int cpu_config_tdp_levels(void)
{
msr_t platform_info;
@ -304,5 +227,4 @@ static const struct cpu_device_id cpu_table[] = {
static const struct cpu_driver driver __cpu_driver = {
.ops = &cpu_dev_ops,
.id_table = cpu_table,
.cstates = cstate_map,
};