Remaining boards are Kconfig'd now. Whether they work
or not still depends on how close the configuration options are to what they should be. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4751 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Patrick Georgi
parent
91ff0df627
commit
00f0267f78
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@ -1,2 +1,3 @@
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subdirs-y += pci
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subdirs-y += generic/debug
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subdirs-y += ati/ragexl
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@ -0,0 +1 @@
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obj-$(CONFIG_DRIVERS_GENERIC_DEBUG) += debug_dev.o
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@ -2,8 +2,13 @@ choice
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prompt "Mainboard model"
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depends on VENDOR_AMD
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source "src/mainboard/amd/serengeti_cheetah/Kconfig"
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source "src/mainboard/amd/db800/Kconfig"
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source "src/mainboard/amd/dbm690t/Kconfig"
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source "src/mainboard/amd/norwich/Kconfig"
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source "src/mainboard/amd/pistachio/Kconfig"
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source "src/mainboard/amd/rumba/Kconfig"
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source "src/mainboard/amd/serengeti_cheetah/Kconfig"
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source "src/mainboard/amd/serengeti_cheetah_fam10/Kconfig"
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endchoice
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@ -0,0 +1,48 @@
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config BOARD_AMD_DB800
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bool "DB800"
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select ARCH_X86
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select CPU_AMD_LX
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select NORTHBRIDGE_AMD_LX
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select SOUTHBRIDGE_AMD_CS5536
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select SUPERIO_WINBOND_W83627HF
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select HAVE_PIRQ_TABLE
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select PIRQ_ROUTE
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select UDELAY_TSC
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select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
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select USE_DCACHE_RAM
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select USE_PRINTK_IN_CAR
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config MAINBOARD_DIR
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string
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default amd/db800
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depends on BOARD_AMD_DB800
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config MAINBOARD_PART_NUMBER
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string
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default "DB800"
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depends on BOARD_AMD_DB800
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config HAVE_OPTION_TABLE
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bool
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default n
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depends on BOARD_AMD_DB800
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config IRQ_SLOT_COUNT
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int
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default 6
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depends on BOARD_AMD_DB800
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config DCACHE_RAM_BASE
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hex
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default 0xc8000
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depends on BOARD_AMD_DB800
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config DCACHE_RAM_SIZE
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hex
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default 0x8000
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depends on BOARD_AMD_DB800
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config RAMBASE
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hex
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default 0x4000
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depends on BOARD_AMD_DB800
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@ -0,0 +1,31 @@
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driver-y += mainboard.o
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# Needed by irq_tables and mptable and acpi_tables.
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obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
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# This is part of the conversion to init-obj and away from included code.
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initobj-y += crt0.o
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# FIXME in $(top)/Makefile
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crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
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crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
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crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
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crt0-y += ../../../../src/arch/i386/lib/id.inc
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crt0-y += ../../../../src/cpu/amd/model_lx/cache_as_ram.inc
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crt0-y += auto.inc
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ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
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ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
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ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
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ldscript-y += ../../../../src/arch/i386/lib/id.lds
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ldscript-y += ../../../../src/arch/i386/lib/failover.lds
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ifdef POST_EVALUATION
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$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c
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$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@
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perl -e 's/\.rodata/.rom.data/g' -pi $@
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perl -e 's/\.text/.section .rom.text/g' -pi $@
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endif
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@ -0,0 +1,104 @@
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config BOARD_AMD_DBM690T
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bool "DBM690T"
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select ARCH_X86
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select CPU_AMD_K8
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select CPU_AMD_SOCKET_S1G1
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select NORTHBRIDGE_AMD_AMDK8
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select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
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select SOUTHBRIDGE_AMD_RS690
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select SOUTHBRIDGE_AMD_SB600
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select SUPERIO_ITE_IT8712F
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select HAVE_PIRQ_TABLE
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select USE_PRINTK_IN_CAR
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select USE_DCACHE_RAM
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select HAVE_HARD_RESET
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select IOAPIC
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select AP_CODE_IN_CAR
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select SB_HT_CHAIN_UNITID_OFFSET_ONLY
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select WAIT_BEFORE_CPUS_INIT
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select HAVE_ACPI_TABLES
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config MAINBOARD_DIR
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string
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default amd/dbm690t
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depends on BOARD_AMD_DBM690T
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config DCACHE_RAM_BASE
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hex
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default 0xc8000
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depends on BOARD_AMD_DBM690T
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config DCACHE_RAM_SIZE
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hex
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default 0x08000
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depends on BOARD_AMD_DBM690T
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config DCACHE_RAM_GLOBAL_VAR_SIZE
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hex
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default 0x01000
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depends on BOARD_AMD_DBM690T
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config APIC_ID_OFFSET
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hex
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default 0x8
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depends on BOARD_AMD_DBM690T
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config LB_CKS_RANGE_END
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int
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default 122
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depends on BOARD_AMD_DBM690T
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config LB_CKS_LOC
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int
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default 123
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depends on BOARD_AMD_DBM690T
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config MAINBOARD_PART_NUMBER
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string
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default "DBM690T"
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depends on BOARD_AMD_DBM690T
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config HW_MEM_HOLE_SIZEK
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hex
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default 0x100000
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depends on BOARD_AMD_DBM690T
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config MAX_CPUS
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int
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default 2
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depends on BOARD_AMD_DBM690T
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config MAX_PHYSICAL_CPUS
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int
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default 1
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depends on BOARD_AMD_DBM690T
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config HW_MEM_HOLE_SIZE_AUTO_INC
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bool
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default n
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depends on BOARD_AMD_DBM690T
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config SB_HT_CHAIN_ON_BUS0
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int
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default 2
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depends on BOARD_AMD_DBM690T
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x6
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depends on BOARD_AMD_DBM690T
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config HT_CHAIN_UNITID_BASE
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hex
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default 0xa
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depends on BOARD_AMD_DBM690T
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config USE_INIT
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bool
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default n
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depends on BOARD_AMD_DBM690T
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config IRQ_SLOT_COUNT
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int
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default 11
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depends on BOARD_AMD_DBM690T
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@ -0,0 +1,64 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2008 coresystems GmbH
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##
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## This program is free software; you can redistribute it and/or
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||||
## modify it under the terms of the GNU General Public License as
|
||||
## published by the Free Software Foundation; version 2 of
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## the License.
|
||||
##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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## MA 02110-1301 USA
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##
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driver-y += mainboard.o
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# Needed by irq_tables and mptable and acpi_tables.
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obj-y += get_bus_conf.o
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obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
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obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
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obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o
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obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o
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obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o
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# This is part of the conversion to init-obj and away from included code.
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initobj-y += crt0.o
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# FIXME in $(top)/Makefile
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crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
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crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
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crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
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crt0-y += ../../../../src/arch/i386/lib/id.inc
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crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
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crt0-y += auto.inc
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ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
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ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
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ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
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ldscript-y += ../../../../src/arch/i386/lib/id.lds
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ldscript-y += ../../../../src/arch/i386/lib/failover.lds
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ifdef POST_EVALUATION
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$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/acpi/dsdt.asl
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iasl -p $(obj)/dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/acpi/dsdt.asl
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mv $(obj)/dsdt.hex $@
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$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
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$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
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||||
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||||
$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h
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||||
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@
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||||
perl -e 's/\.rodata/.rom.data/g' -pi $@
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||||
perl -e 's/\.text/.section .rom.text/g' -pi $@
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||||
endif
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||||
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@ -0,0 +1,47 @@
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config BOARD_AMD_NORWICH
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bool "Norwich"
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select ARCH_X86
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select CPU_AMD_LX
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select NORTHBRIDGE_AMD_LX
|
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select SOUTHBRIDGE_AMD_CS5536
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select HAVE_PIRQ_TABLE
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select PIRQ_ROUTE
|
||||
select UDELAY_TSC
|
||||
select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
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||||
select USE_DCACHE_RAM
|
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select USE_PRINTK_IN_CAR
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||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default amd/norwich
|
||||
depends on BOARD_AMD_NORWICH
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "NORWICH"
|
||||
depends on BOARD_AMD_NORWICH
|
||||
|
||||
config HAVE_OPTION_TABLE
|
||||
bool
|
||||
default n
|
||||
depends on BOARD_AMD_NORWICH
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 6
|
||||
depends on BOARD_AMD_NORWICH
|
||||
|
||||
config DCACHE_RAM_BASE
|
||||
hex
|
||||
default 0xc8000
|
||||
depends on BOARD_AMD_NORWICH
|
||||
|
||||
config DCACHE_RAM_SIZE
|
||||
hex
|
||||
default 0x8000
|
||||
depends on BOARD_AMD_NORWICH
|
||||
|
||||
config RAMBASE
|
||||
hex
|
||||
default 0x4000
|
||||
depends on BOARD_AMD_NORWICH
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
driver-y += mainboard.o
|
||||
|
||||
# Needed by irq_tables and mptable and acpi_tables.
|
||||
obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
|
||||
|
||||
# This is part of the conversion to init-obj and away from included code.
|
||||
|
||||
initobj-y += crt0.o
|
||||
# FIXME in $(top)/Makefile
|
||||
crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
|
||||
crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
|
||||
crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
|
||||
crt0-y += ../../../../src/arch/i386/lib/id.inc
|
||||
crt0-y += ../../../../src/cpu/amd/model_lx/cache_as_ram.inc
|
||||
crt0-y += auto.inc
|
||||
|
||||
ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
|
||||
ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
|
||||
ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
|
||||
ldscript-y += ../../../../src/arch/i386/lib/id.lds
|
||||
ldscript-y += ../../../../src/arch/i386/lib/failover.lds
|
||||
|
||||
ifdef POST_EVALUATION
|
||||
|
||||
$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c
|
||||
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@
|
||||
perl -e 's/\.rodata/.rom.data/g' -pi $@
|
||||
perl -e 's/\.text/.section .rom.text/g' -pi $@
|
||||
|
||||
endif
|
||||
|
||||
|
|
@ -0,0 +1,103 @@
|
|||
config BOARD_AMD_PISTACHIO
|
||||
bool "Pistachio"
|
||||
select ARCH_X86
|
||||
select CPU_AMD_K8
|
||||
select CPU_AMD_SOCKET_AM2
|
||||
select NORTHBRIDGE_AMD_AMDK8
|
||||
select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
|
||||
select SOUTHBRIDGE_AMD_RS690
|
||||
select SOUTHBRIDGE_AMD_SB600
|
||||
select HAVE_PIRQ_TABLE
|
||||
select USE_PRINTK_IN_CAR
|
||||
select USE_DCACHE_RAM
|
||||
select HAVE_HARD_RESET
|
||||
select IOAPIC
|
||||
select AP_CODE_IN_CAR
|
||||
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
||||
select WAIT_BEFORE_CPUS_INIT
|
||||
select HAVE_ACPI_TABLES
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default amd/pistachio
|
||||
depends on BOARD_AMD_PISTACHIO
|
||||
|
||||
config DCACHE_RAM_BASE
|
||||
hex
|
||||
default 0xc8000
|
||||
depends on BOARD_AMD_PISTACHIO
|
||||
|
||||
config DCACHE_RAM_SIZE
|
||||
hex
|
||||
default 0x08000
|
||||
depends on BOARD_AMD_PISTACHIO
|
||||
|
||||
config DCACHE_RAM_GLOBAL_VAR_SIZE
|
||||
hex
|
||||
default 0x01000
|
||||
depends on BOARD_AMD_PISTACHIO
|
||||
|
||||
config APIC_ID_OFFSET
|
||||
hex
|
||||
default 0x8
|
||||
depends on BOARD_AMD_PISTACHIO
|
||||
|
||||
config LB_CKS_RANGE_END
|
||||
int
|
||||
default 122
|
||||
depends on BOARD_AMD_PISTACHIO
|
||||
|
||||
config LB_CKS_LOC
|
||||
int
|
||||
default 123
|
||||
depends on BOARD_AMD_PISTACHIO
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "PISTACHIO"
|
||||
depends on BOARD_AMD_PISTACHIO
|
||||
|
||||
config HW_MEM_HOLE_SIZEK
|
||||
hex
|
||||
default 0x100000
|
||||
depends on BOARD_AMD_PISTACHIO
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 2
|
||||
depends on BOARD_AMD_PISTACHIO
|
||||
|
||||
config MAX_PHYSICAL_CPUS
|
||||
int
|
||||
default 1
|
||||
depends on BOARD_AMD_PISTACHIO
|
||||
|
||||
config HW_MEM_HOLE_SIZE_AUTO_INC
|
||||
bool
|
||||
default n
|
||||
depends on BOARD_AMD_PISTACHIO
|
||||
|
||||
config SB_HT_CHAIN_ON_BUS0
|
||||
int
|
||||
default 2
|
||||
depends on BOARD_AMD_PISTACHIO
|
||||
|
||||
config HT_CHAIN_END_UNITID_BASE
|
||||
hex
|
||||
default 0x6
|
||||
depends on BOARD_AMD_PISTACHIO
|
||||
|
||||
config HT_CHAIN_UNITID_BASE
|
||||
hex
|
||||
default 0xa
|
||||
depends on BOARD_AMD_PISTACHIO
|
||||
|
||||
config USE_INIT
|
||||
bool
|
||||
default n
|
||||
depends on BOARD_AMD_PISTACHIO
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 11
|
||||
depends on BOARD_AMD_PISTACHIO
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007-2008 coresystems GmbH
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or
|
||||
## modify it under the terms of the GNU General Public License as
|
||||
## published by the Free Software Foundation; version 2 of
|
||||
## the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
## MA 02110-1301 USA
|
||||
##
|
||||
|
||||
driver-y += mainboard.o
|
||||
|
||||
# Needed by irq_tables and mptable and acpi_tables.
|
||||
obj-y += get_bus_conf.o
|
||||
obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
|
||||
obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
|
||||
obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o
|
||||
obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o
|
||||
obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o
|
||||
|
||||
# This is part of the conversion to init-obj and away from included code.
|
||||
|
||||
initobj-y += crt0.o
|
||||
# FIXME in $(top)/Makefile
|
||||
crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
|
||||
crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
|
||||
crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
|
||||
crt0-y += ../../../../src/arch/i386/lib/id.inc
|
||||
crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
|
||||
crt0-y += auto.inc
|
||||
|
||||
ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
|
||||
ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
|
||||
ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
|
||||
ldscript-y += ../../../../src/arch/i386/lib/id.lds
|
||||
ldscript-y += ../../../../src/arch/i386/lib/failover.lds
|
||||
|
||||
ifdef POST_EVALUATION
|
||||
|
||||
$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/acpi/dsdt.asl
|
||||
iasl -p $(obj)/dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/acpi/dsdt.asl
|
||||
mv $(obj)/dsdt.hex $@
|
||||
|
||||
$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
|
||||
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
|
||||
|
||||
$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h
|
||||
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@
|
||||
perl -e 's/\.rodata/.rom.data/g' -pi $@
|
||||
perl -e 's/\.text/.section .rom.text/g' -pi $@
|
||||
|
||||
endif
|
||||
|
||||
|
|
@ -0,0 +1,116 @@
|
|||
config BOARD_AMD_SERENGETI_CHEETAH_FAM10
|
||||
bool "Serengeti Cheetah (Fam10)"
|
||||
select ARCH_X86
|
||||
select CPU_AMD_FAM10
|
||||
select CPU_AMD_SOCKET_F_1207
|
||||
select NORTHBRIDGE_AMD_AMDFAM10
|
||||
select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX
|
||||
select SOUTHBRIDGE_AMD_AMD8111
|
||||
select SOUTHBRIDGE_AMD_AMD8132
|
||||
select SUPERIO_WINBOND_W83627HF
|
||||
select HAVE_PIRQ_TABLE
|
||||
select USE_PRINTK_IN_CAR
|
||||
select USE_DCACHE_RAM
|
||||
select HAVE_HARD_RESET
|
||||
select IOAPIC
|
||||
select AP_CODE_IN_CAR
|
||||
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
||||
select WAIT_BEFORE_CPUS_INIT
|
||||
select AMDMCT
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default amd/serengeti_cheetah_fam10
|
||||
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
|
||||
|
||||
config DCACHE_RAM_BASE
|
||||
hex
|
||||
default 0xc8000
|
||||
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
|
||||
|
||||
config DCACHE_RAM_SIZE
|
||||
hex
|
||||
default 0x08000
|
||||
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
|
||||
|
||||
config DCACHE_RAM_GLOBAL_VAR_SIZE
|
||||
hex
|
||||
default 0x01000
|
||||
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
|
||||
|
||||
config APIC_ID_OFFSET
|
||||
hex
|
||||
default 0x8
|
||||
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
|
||||
|
||||
config LB_CKS_RANGE_END
|
||||
int
|
||||
default 122
|
||||
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
|
||||
|
||||
config LB_CKS_LOC
|
||||
int
|
||||
default 123
|
||||
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "Serengeti-Cheetah-Fam10"
|
||||
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
|
||||
|
||||
config HW_MEM_HOLE_SIZEK
|
||||
hex
|
||||
default 0x100000
|
||||
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
|
||||
|
||||
# 6 * MAX_PHYSICAL_CPUS
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 48
|
||||
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
|
||||
|
||||
config MAX_PHYSICAL_CPUS
|
||||
int
|
||||
default 8
|
||||
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
|
||||
|
||||
config HW_MEM_HOLE_SIZE_AUTO_INC
|
||||
bool
|
||||
default n
|
||||
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
|
||||
|
||||
config SB_HT_CHAIN_ON_BUS0
|
||||
int
|
||||
default 2
|
||||
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
|
||||
|
||||
config HT_CHAIN_END_UNITID_BASE
|
||||
hex
|
||||
default 0x6
|
||||
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
|
||||
|
||||
config HT_CHAIN_UNITID_BASE
|
||||
hex
|
||||
default 0xa
|
||||
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
|
||||
|
||||
config USE_INIT
|
||||
bool
|
||||
default n
|
||||
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
|
||||
|
||||
config SERIAL_CPU_INIT
|
||||
bool
|
||||
default n
|
||||
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 11
|
||||
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
|
||||
|
||||
config AMD_UCODE_PATCH_FILE
|
||||
string
|
||||
default "mc_patch_01000095.h"
|
||||
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
|
||||
|
||||
|
|
@ -0,0 +1,85 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007-2008 coresystems GmbH
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or
|
||||
## modify it under the terms of the GNU General Public License as
|
||||
## published by the Free Software Foundation; version 2 of
|
||||
## the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
## MA 02110-1301 USA
|
||||
##
|
||||
|
||||
driver-y += mainboard.o
|
||||
|
||||
# Needed by irq_tables and mptable and acpi_tables.
|
||||
obj-y += get_bus_conf.o
|
||||
obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
|
||||
obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
|
||||
obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o
|
||||
obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o
|
||||
obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o
|
||||
|
||||
# ./ssdt.o is in northbridge/amd/amdk8/Config.lb
|
||||
obj-$(CONFIG_ACPI_SSDTX_NUM) += ssdt2.o
|
||||
obj-$(CONFIG_ACPI_SSDTX_NUM) += ssdt3.o
|
||||
obj-$(CONFIG_ACPI_SSDTX_NUM) += ssdt4.o
|
||||
driver-y += ../../../drivers/i2c/i2cmux/i2cmux.o
|
||||
|
||||
# This is part of the conversion to init-obj and away from included code.
|
||||
|
||||
initobj-y += crt0.o
|
||||
# FIXME in $(top)/Makefile
|
||||
crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
|
||||
crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
|
||||
crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
|
||||
crt0-y += ../../../../src/arch/i386/lib/id.inc
|
||||
crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
|
||||
crt0-y += auto.inc
|
||||
|
||||
ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
|
||||
ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
|
||||
ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
|
||||
ldscript-y += ../../../../src/arch/i386/lib/id.lds
|
||||
ldscript-y += ../../../../src/arch/i386/lib/failover.lds
|
||||
|
||||
ifdef POST_EVALUATION
|
||||
|
||||
$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl
|
||||
iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl
|
||||
mv dsdt.hex $@
|
||||
|
||||
$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
|
||||
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
|
||||
|
||||
$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl
|
||||
iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl
|
||||
perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex
|
||||
mv pci2.hex ssdt2.c
|
||||
|
||||
$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl"
|
||||
iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/
|
||||
perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex
|
||||
mv pci3.hex ssdt3.c
|
||||
|
||||
$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl"
|
||||
iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl
|
||||
perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex
|
||||
mv pci4.hex ssdt4.c
|
||||
|
||||
$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h
|
||||
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@
|
||||
perl -e 's/\.rodata/.rom.data/g' -pi $@
|
||||
perl -e 's/\.text/.section .rom.text/g' -pi $@
|
||||
|
||||
endif
|
||||
|
||||
|
|
@ -1 +1,10 @@
|
|||
#
|
||||
choice
|
||||
prompt "Mainboard model"
|
||||
depends on VENDOR_DIGITAL_LOGIC
|
||||
|
||||
source "src/mainboard/digitallogic/adl855pc/Kconfig"
|
||||
source "src/mainboard/digitallogic/msm586seg/Kconfig"
|
||||
source "src/mainboard/digitallogic/msm800sev/Kconfig"
|
||||
|
||||
endchoice
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,24 @@
|
|||
config BOARD_DIGITALLOGIC_ADL855PC
|
||||
bool "ADL855PC"
|
||||
select ARCH_X86
|
||||
select CPU_INTEL_SOCKET_MPGA479M
|
||||
select NORTHBRIDGE_INTEL_I855PM
|
||||
select SOUTHBRIDGE_INTEL_I82801DBM
|
||||
select SUPERIO_WINBOND_W83627HF
|
||||
select HAVE_PIRQ_TABLE
|
||||
select UDELAY_TSC
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default digitallogic/adl855pc
|
||||
depends on BOARD_DIGITALLOGIC_ADL855PC
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "ADL855PC"
|
||||
depends on BOARD_DIGITALLOGIC_ADL855PC
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 5
|
||||
depends on BOARD_DIGITALLOGIC_ADL855PC
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
ROMCCFLAGS := -mcpu=p3 -O
|
||||
include $(src)/mainboard/Makefile.romccboard.inc
|
||||
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
config BOARD_DIGITALLOGIC_MSM586SEG
|
||||
bool "MSM586SEG"
|
||||
select ARCH_X86
|
||||
select CPU_AMD_SC520
|
||||
select HAVE_PIRQ_TABLE
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default digitallogic/msm586seg
|
||||
depends on BOARD_DIGITALLOGIC_MSM586SEG
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "TS5300"
|
||||
depends on BOARD_DIGITALLOGIC_MSM586SEG
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 2
|
||||
depends on BOARD_DIGITALLOGIC_MSM586SEG
|
||||
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
ROMCCFLAGS := -mcpu=i386 -O
|
||||
include $(src)/mainboard/Makefile.romccboard.inc
|
||||
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
config BOARD_DIGITALLOGIC_MSM800SEV
|
||||
bool "MSM800SEV"
|
||||
select ARCH_X86
|
||||
select CPU_AMD_LX
|
||||
select NORTHBRIDGE_AMD_LX
|
||||
select SOUTHBRIDGE_AMD_CS5536
|
||||
select SUPERIO_WINBOND_W83627HF
|
||||
select HAVE_PIRQ_TABLE
|
||||
select PIRQ_ROUTE
|
||||
select UDELAY_TSC
|
||||
select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
|
||||
select USE_DCACHE_RAM
|
||||
select USE_PRINTK_IN_CAR
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default digitallogic/msm800sev
|
||||
depends on BOARD_DIGITALLOGIC_MSM800SEV
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "MSM800SEV"
|
||||
depends on BOARD_DIGITALLOGIC_MSM800SEV
|
||||
|
||||
config HAVE_OPTION_TABLE
|
||||
bool
|
||||
default n
|
||||
depends on BOARD_DIGITALLOGIC_MSM800SEV
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 7
|
||||
depends on BOARD_DIGITALLOGIC_MSM800SEV
|
||||
|
||||
config DCACHE_RAM_BASE
|
||||
hex
|
||||
default 0xc8000
|
||||
depends on BOARD_DIGITALLOGIC_MSM800SEV
|
||||
|
||||
config DCACHE_RAM_SIZE
|
||||
hex
|
||||
default 0x8000
|
||||
depends on BOARD_DIGITALLOGIC_MSM800SEV
|
||||
|
||||
config RAMBASE
|
||||
hex
|
||||
default 0x4000
|
||||
depends on BOARD_DIGITALLOGIC_MSM800SEV
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
driver-y += mainboard.o
|
||||
|
||||
# Needed by irq_tables and mptable and acpi_tables.
|
||||
obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
|
||||
|
||||
# This is part of the conversion to init-obj and away from included code.
|
||||
|
||||
initobj-y += crt0.o
|
||||
# FIXME in $(top)/Makefile
|
||||
crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
|
||||
crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
|
||||
crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
|
||||
crt0-y += ../../../../src/arch/i386/lib/id.inc
|
||||
crt0-y += ../../../../src/cpu/amd/model_lx/cache_as_ram.inc
|
||||
crt0-y += auto.inc
|
||||
|
||||
ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
|
||||
ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
|
||||
ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
|
||||
ldscript-y += ../../../../src/arch/i386/lib/id.lds
|
||||
ldscript-y += ../../../../src/arch/i386/lib/failover.lds
|
||||
|
||||
ifdef POST_EVALUATION
|
||||
|
||||
$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c
|
||||
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@
|
||||
perl -e 's/\.rodata/.rom.data/g' -pi $@
|
||||
perl -e 's/\.text/.section .rom.text/g' -pi $@
|
||||
|
||||
endif
|
||||
|
||||
|
|
@ -3,12 +3,13 @@ choice
|
|||
depends on VENDOR_SUPERMICRO
|
||||
|
||||
source "src/mainboard/supermicro/h8dme/Kconfig"
|
||||
#source "src/mainboard/supermicro/h8dmr/Kconfig"
|
||||
#source "src/mainboard/supermicro/x6dai_g/Kconfig"
|
||||
#source "src/mainboard/supermicro/x6dhe_g/Kconfig"
|
||||
#source "src/mainboard/supermicro/x6dhe_g2/Kconfig"
|
||||
#source "src/mainboard/supermicro/x6dhr_ig/Kconfig"
|
||||
#source "src/mainboard/supermicro/x6dhr_ig2/Kconfig"
|
||||
source "src/mainboard/supermicro/h8dmr/Kconfig"
|
||||
source "src/mainboard/supermicro/h8dmr_fam10/Kconfig"
|
||||
source "src/mainboard/supermicro/x6dai_g/Kconfig"
|
||||
source "src/mainboard/supermicro/x6dhe_g/Kconfig"
|
||||
source "src/mainboard/supermicro/x6dhe_g2/Kconfig"
|
||||
source "src/mainboard/supermicro/x6dhr_ig/Kconfig"
|
||||
source "src/mainboard/supermicro/x6dhr_ig2/Kconfig"
|
||||
|
||||
endchoice
|
||||
|
||||
|
|
|
|||
|
|
@ -60,7 +60,7 @@ config LB_CKS_LOC
|
|||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "ultra40"
|
||||
default "H8DME"
|
||||
depends on BOARD_SUPERMICRO_H8DME
|
||||
|
||||
config HW_MEM_HOLE_SIZEK
|
||||
|
|
|
|||
|
|
@ -0,0 +1,104 @@
|
|||
config BOARD_SUPERMICRO_H8DMR
|
||||
bool "H8DMR"
|
||||
select ARCH_X86
|
||||
select CPU_AMD_K8
|
||||
select CPU_AMD_SOCKET_F
|
||||
select NORTHBRIDGE_AMD_AMDK8
|
||||
select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
|
||||
select SOUTHBRIDGE_NVIDIA_MCP55
|
||||
select SUPERIO_WINBOND_W83627HF
|
||||
select HAVE_PIRQ_TABLE
|
||||
select USE_PRINTK_IN_CAR
|
||||
select USE_DCACHE_RAM
|
||||
select HAVE_HARD_RESET
|
||||
select IOAPIC
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default supermicro/h8dmr
|
||||
depends on BOARD_SUPERMICRO_H8DMR
|
||||
|
||||
config DCACHE_RAM_BASE
|
||||
hex
|
||||
default 0xc8000
|
||||
depends on BOARD_SUPERMICRO_H8DMR
|
||||
|
||||
config DCACHE_RAM_SIZE
|
||||
hex
|
||||
default 0x08000
|
||||
depends on BOARD_SUPERMICRO_H8DMR
|
||||
|
||||
config DCACHE_RAM_GLOBAL_VAR_SIZE
|
||||
hex
|
||||
default 0x01000
|
||||
depends on BOARD_SUPERMICRO_H8DMR
|
||||
|
||||
config APIC_ID_OFFSET
|
||||
hex
|
||||
default 0x10
|
||||
depends on BOARD_SUPERMICRO_H8DMR
|
||||
|
||||
config SB_HT_CHAIN_ON_BUS0
|
||||
int
|
||||
default 2
|
||||
depends on BOARD_SUPERMICRO_H8DMR
|
||||
|
||||
config SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
||||
bool
|
||||
default n
|
||||
depends on BOARD_SUPERMICRO_H8DMR
|
||||
|
||||
config LB_CKS_RANGE_END
|
||||
int
|
||||
default 122
|
||||
depends on BOARD_SUPERMICRO_H8DMR
|
||||
|
||||
config LB_CKS_LOC
|
||||
int
|
||||
default 123
|
||||
depends on BOARD_SUPERMICRO_H8DMR
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "H8DMR"
|
||||
depends on BOARD_SUPERMICRO_H8DMR
|
||||
|
||||
config HW_MEM_HOLE_SIZEK
|
||||
hex
|
||||
default 0x100000
|
||||
depends on BOARD_SUPERMICRO_H8DMR
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 4
|
||||
depends on BOARD_SUPERMICRO_H8DMR
|
||||
|
||||
config MAX_PHYSICAL_CPUS
|
||||
int
|
||||
default 2
|
||||
depends on BOARD_SUPERMICRO_H8DMR
|
||||
|
||||
config HT_CHAIN_END_UNITID_BASE
|
||||
hex
|
||||
default 0x0
|
||||
depends on BOARD_SUPERMICRO_H8DMR
|
||||
|
||||
config HT_CHAIN_UNITID_BASE
|
||||
hex
|
||||
default 0x0
|
||||
depends on BOARD_SUPERMICRO_H8DMR
|
||||
|
||||
config USE_INIT
|
||||
bool
|
||||
default n
|
||||
depends on BOARD_SUPERMICRO_H8DMR
|
||||
|
||||
config SB_HT_CHAIN_ON_BUS0
|
||||
int
|
||||
default 2
|
||||
depends on BOARD_SUPERMICRO_H8DMR
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 11
|
||||
depends on BOARD_SUPERMICRO_H8DMR
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007-2008 coresystems GmbH
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or
|
||||
## modify it under the terms of the GNU General Public License as
|
||||
## published by the Free Software Foundation; version 2 of
|
||||
## the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
## MA 02110-1301 USA
|
||||
##
|
||||
|
||||
driver-y += mainboard.o
|
||||
|
||||
# Needed by irq_tables and mptable and acpi_tables.
|
||||
obj-y += get_bus_conf.o
|
||||
obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
|
||||
obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
|
||||
|
||||
# This is part of the conversion to init-obj and away from included code.
|
||||
|
||||
initobj-y += crt0.o
|
||||
# FIXME in $(top)/Makefile
|
||||
crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
|
||||
crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
|
||||
crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
|
||||
crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
|
||||
crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc
|
||||
crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
|
||||
crt0-y += auto.inc
|
||||
|
||||
ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
|
||||
ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
|
||||
ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
|
||||
ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
|
||||
ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds
|
||||
ldscript-y += ../../../../src/arch/i386/lib/failover.lds
|
||||
|
||||
ifdef POST_EVALUATION
|
||||
|
||||
$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl
|
||||
iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl
|
||||
mv dsdt.hex $@
|
||||
|
||||
$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
|
||||
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
|
||||
|
||||
$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl
|
||||
iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl
|
||||
perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex
|
||||
mv pci2.hex ssdt2.c
|
||||
|
||||
$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl"
|
||||
iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/
|
||||
perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex
|
||||
mv pci3.hex ssdt3.c
|
||||
|
||||
$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl"
|
||||
iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl
|
||||
perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex
|
||||
mv pci4.hex ssdt4.c
|
||||
|
||||
$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h
|
||||
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@
|
||||
perl -e 's/\.rodata/.rom.data/g' -pi $@
|
||||
perl -e 's/\.text/.section .rom.text/g' -pi $@
|
||||
|
||||
endif
|
||||
|
||||
|
|
@ -0,0 +1,110 @@
|
|||
config BOARD_SUPERMICRO_H8DMR_FAM10
|
||||
bool "H8DMR_FAM10 (Fam10)"
|
||||
select ARCH_X86
|
||||
select CPU_AMD_FAM10
|
||||
select CPU_AMD_SOCKET_F_1207
|
||||
select NORTHBRIDGE_AMD_AMDFAM10
|
||||
select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX
|
||||
select SOUTHBRIDGE_NVIDIA_MCP55
|
||||
select SUPERIO_WINBOND_W83627HF
|
||||
select HAVE_PIRQ_TABLE
|
||||
select USE_PRINTK_IN_CAR
|
||||
select USE_DCACHE_RAM
|
||||
select HAVE_HARD_RESET
|
||||
select IOAPIC
|
||||
select AMDMCT
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default supermicro/h8dmr_fam10
|
||||
depends on BOARD_SUPERMICRO_H8DMR_FAM10
|
||||
|
||||
config DCACHE_RAM_BASE
|
||||
hex
|
||||
default 0xc8000
|
||||
depends on BOARD_SUPERMICRO_H8DMR_FAM10
|
||||
|
||||
config DCACHE_RAM_SIZE
|
||||
hex
|
||||
default 0x08000
|
||||
depends on BOARD_SUPERMICRO_H8DMR_FAM10
|
||||
|
||||
config DCACHE_RAM_GLOBAL_VAR_SIZE
|
||||
hex
|
||||
default 0x01000
|
||||
depends on BOARD_SUPERMICRO_H8DMR_FAM10
|
||||
|
||||
config APIC_ID_OFFSET
|
||||
hex
|
||||
default 0x10
|
||||
depends on BOARD_SUPERMICRO_H8DMR_FAM10
|
||||
|
||||
config SB_HT_CHAIN_ON_BUS0
|
||||
int
|
||||
default 2
|
||||
depends on BOARD_SUPERMICRO_H8DMR_FAM10
|
||||
|
||||
config SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
||||
bool
|
||||
default n
|
||||
depends on BOARD_SUPERMICRO_H8DMR_FAM10
|
||||
|
||||
config LB_CKS_RANGE_END
|
||||
int
|
||||
default 122
|
||||
depends on BOARD_SUPERMICRO_H8DMR_FAM10
|
||||
|
||||
config LB_CKS_LOC
|
||||
int
|
||||
default 123
|
||||
depends on BOARD_SUPERMICRO_H8DMR_FAM10
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "H8DMR_FAM10 FAM10"
|
||||
depends on BOARD_SUPERMICRO_H8DMR_FAM10
|
||||
|
||||
config HW_MEM_HOLE_SIZEK
|
||||
hex
|
||||
default 0x100000
|
||||
depends on BOARD_SUPERMICRO_H8DMR_FAM10
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 4
|
||||
depends on BOARD_SUPERMICRO_H8DMR_FAM10
|
||||
|
||||
config MAX_PHYSICAL_CPUS
|
||||
int
|
||||
default 2
|
||||
depends on BOARD_SUPERMICRO_H8DMR_FAM10
|
||||
|
||||
config HT_CHAIN_END_UNITID_BASE
|
||||
hex
|
||||
default 0x0
|
||||
depends on BOARD_SUPERMICRO_H8DMR_FAM10
|
||||
|
||||
config HT_CHAIN_UNITID_BASE
|
||||
hex
|
||||
default 0x0
|
||||
depends on BOARD_SUPERMICRO_H8DMR_FAM10
|
||||
|
||||
config USE_INIT
|
||||
bool
|
||||
default n
|
||||
depends on BOARD_SUPERMICRO_H8DMR_FAM10
|
||||
|
||||
config SB_HT_CHAIN_ON_BUS0
|
||||
int
|
||||
default 2
|
||||
depends on BOARD_SUPERMICRO_H8DMR_FAM10
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 11
|
||||
depends on BOARD_SUPERMICRO_H8DMR_FAM10
|
||||
|
||||
config AMD_UCODE_PATCH_FILE
|
||||
string
|
||||
default "mc_patch_0100009f.h"
|
||||
depends on BOARD_SUPERMICRO_H8DMR_FAM10
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007-2008 coresystems GmbH
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or
|
||||
## modify it under the terms of the GNU General Public License as
|
||||
## published by the Free Software Foundation; version 2 of
|
||||
## the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
## MA 02110-1301 USA
|
||||
##
|
||||
|
||||
driver-y += mainboard.o
|
||||
|
||||
# Needed by irq_tables and mptable and acpi_tables.
|
||||
obj-y += get_bus_conf.o
|
||||
obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
|
||||
obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
|
||||
|
||||
# This is part of the conversion to init-obj and away from included code.
|
||||
|
||||
initobj-y += crt0.o
|
||||
# FIXME in $(top)/Makefile
|
||||
crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
|
||||
crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
|
||||
crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
|
||||
crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
|
||||
crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc
|
||||
crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
|
||||
crt0-y += auto.inc
|
||||
|
||||
ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
|
||||
ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
|
||||
ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
|
||||
ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
|
||||
ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds
|
||||
ldscript-y += ../../../../src/arch/i386/lib/failover.lds
|
||||
|
||||
ifdef POST_EVALUATION
|
||||
|
||||
$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl
|
||||
iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl
|
||||
mv dsdt.hex $@
|
||||
|
||||
$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
|
||||
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
|
||||
|
||||
$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl
|
||||
iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl
|
||||
perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex
|
||||
mv pci2.hex ssdt2.c
|
||||
|
||||
$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl"
|
||||
iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/
|
||||
perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex
|
||||
mv pci3.hex ssdt3.c
|
||||
|
||||
$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl"
|
||||
iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl
|
||||
perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex
|
||||
mv pci4.hex ssdt4.c
|
||||
|
||||
$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h
|
||||
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@
|
||||
perl -e 's/\.rodata/.rom.data/g' -pi $@
|
||||
perl -e 's/\.text/.section .rom.text/g' -pi $@
|
||||
|
||||
endif
|
||||
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
config BOARD_SUPERMICRO_X6DAI_G
|
||||
bool "X6DAI-G"
|
||||
select ARCH_X86
|
||||
select CPU_INTEL_SOCKET_MPGA604
|
||||
select NORTHBRIDGE_INTEL_E7525
|
||||
select SOUTHBRIDGE_INTEL_ESB6300
|
||||
select SUPERIO_WINBOND_W83627HF
|
||||
select PIRQ_TABLE
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default supermicro/x6dai_g
|
||||
depends on BOARD_SUPERMICRO_X6DAI_G
|
||||
|
||||
config LB_CKS_RANGE_END
|
||||
int
|
||||
default 122
|
||||
depends on BOARD_SUPERMICRO_X6DAI_G
|
||||
|
||||
config LB_CKS_LOC
|
||||
int
|
||||
default 123
|
||||
depends on BOARD_SUPERMICRO_X6DAI_G
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "X6DAI_G"
|
||||
depends on BOARD_SUPERMICRO_X6DAI_G
|
||||
|
||||
config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
|
||||
hex
|
||||
default 0x15d9
|
||||
depends on BOARD_SUPERMICRO_X6DAI_G
|
||||
|
||||
config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
|
||||
hex
|
||||
default 0x6780
|
||||
depends on BOARD_SUPERMICRO_X6DAI_G
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 4
|
||||
depends on BOARD_SUPERMICRO_X6DAI_G
|
||||
|
||||
config USE_INIT
|
||||
bool
|
||||
default n
|
||||
depends on BOARD_SUPERMICRO_X6DAI_G
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 15
|
||||
depends on BOARD_SUPERMICRO_X6DAI_G
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
ROMCCFLAGS=-mcpu=p4 -O2
|
||||
|
||||
include $(src)/mainboard/Makefile.romccboard.inc
|
||||
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
config BOARD_SUPERMICRO_X6DHE_G
|
||||
bool "X6DHE-G"
|
||||
select ARCH_X86
|
||||
select CPU_INTEL_SOCKET_MPGA604
|
||||
select NORTHBRIDGE_INTEL_E7520
|
||||
select SOUTHBRIDGE_INTEL_ESB6300
|
||||
select SOUTHBRIDGE_INTEL_PXHD
|
||||
select SUPERIO_WINBOND_W83627HF
|
||||
select PIRQ_TABLE
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default supermicro/x6dhe_g
|
||||
depends on BOARD_SUPERMICRO_X6DHE_G
|
||||
|
||||
config LB_CKS_RANGE_END
|
||||
int
|
||||
default 122
|
||||
depends on BOARD_SUPERMICRO_X6DHE_G
|
||||
|
||||
config LB_CKS_LOC
|
||||
int
|
||||
default 123
|
||||
depends on BOARD_SUPERMICRO_X6DHE_G
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "X6DHE_G"
|
||||
depends on BOARD_SUPERMICRO_X6DHE_G
|
||||
|
||||
config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
|
||||
hex
|
||||
default 0x15d9
|
||||
depends on BOARD_SUPERMICRO_X6DHE_G
|
||||
|
||||
config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
|
||||
hex
|
||||
default 0x6780
|
||||
depends on BOARD_SUPERMICRO_X6DHE_G
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 4
|
||||
depends on BOARD_SUPERMICRO_X6DHE_G
|
||||
|
||||
config USE_INIT
|
||||
bool
|
||||
default n
|
||||
depends on BOARD_SUPERMICRO_X6DHE_G
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 15
|
||||
depends on BOARD_SUPERMICRO_X6DHE_G
|
||||
|
||||
config DRIVERS_GENERIC_DEBUG
|
||||
bool
|
||||
default y
|
||||
depends on BOARD_SUPERMICRO_X6DHE_G
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
ROMCCFLAGS=-mcpu=p4 -O2
|
||||
|
||||
include $(src)/mainboard/Makefile.romccboard.inc
|
||||
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
config BOARD_SUPERMICRO_X6DHE_G2
|
||||
bool "X6DAI-G"
|
||||
select ARCH_X86
|
||||
select CPU_INTEL_SOCKET_MPGA604
|
||||
select NORTHBRIDGE_INTEL_E7520
|
||||
select SOUTHBRIDGE_INTEL_I82801ER
|
||||
select SOUTHBRIDGE_INTEL_PXHD
|
||||
select SUPERIO_NSC_PC87427
|
||||
select PIRQ_TABLE
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default supermicro/x6dhe_g2
|
||||
depends on BOARD_SUPERMICRO_X6DHE_G2
|
||||
|
||||
config LB_CKS_RANGE_END
|
||||
int
|
||||
default 122
|
||||
depends on BOARD_SUPERMICRO_X6DHE_G2
|
||||
|
||||
config LB_CKS_LOC
|
||||
int
|
||||
default 123
|
||||
depends on BOARD_SUPERMICRO_X6DHE_G2
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "X6DHE_G2"
|
||||
depends on BOARD_SUPERMICRO_X6DHE_G2
|
||||
|
||||
config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
|
||||
hex
|
||||
default 0x15d9
|
||||
depends on BOARD_SUPERMICRO_X6DHE_G2
|
||||
|
||||
config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
|
||||
hex
|
||||
default 0x6780
|
||||
depends on BOARD_SUPERMICRO_X6DHE_G2
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 4
|
||||
depends on BOARD_SUPERMICRO_X6DHE_G2
|
||||
|
||||
config USE_INIT
|
||||
bool
|
||||
default n
|
||||
depends on BOARD_SUPERMICRO_X6DHE_G2
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 15
|
||||
depends on BOARD_SUPERMICRO_X6DHE_G2
|
||||
|
||||
config DRIVERS_GENERIC_DEBUG
|
||||
bool
|
||||
default y
|
||||
depends on BOARD_SUPERMICRO_X6DHE_G2
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
ROMCCFLAGS=-mcpu=p4 -O2
|
||||
|
||||
include $(src)/mainboard/Makefile.romccboard.inc
|
||||
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
config BOARD_SUPERMICRO_X6DHR_IG
|
||||
bool "X6DHR-IG"
|
||||
select ARCH_X86
|
||||
select CPU_INTEL_SOCKET_MPGA604
|
||||
select NORTHBRIDGE_INTEL_E7520
|
||||
select SOUTHBRIDGE_INTEL_I82801ER
|
||||
select SOUTHBRIDGE_INTEL_PXHD
|
||||
select SUPERIO_WINBOND_W83627HF
|
||||
select PIRQ_TABLE
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default supermicro/x6dhr_ig
|
||||
depends on BOARD_SUPERMICRO_X6DHR_IG
|
||||
|
||||
config LB_CKS_RANGE_END
|
||||
int
|
||||
default 122
|
||||
depends on BOARD_SUPERMICRO_X6DHR_IG
|
||||
|
||||
config LB_CKS_LOC
|
||||
int
|
||||
default 123
|
||||
depends on BOARD_SUPERMICRO_X6DHR_IG
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "X6DHR_IG"
|
||||
depends on BOARD_SUPERMICRO_X6DHR_IG
|
||||
|
||||
config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
|
||||
hex
|
||||
default 0x15d9
|
||||
depends on BOARD_SUPERMICRO_X6DHR_IG
|
||||
|
||||
config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
|
||||
hex
|
||||
default 0x6780
|
||||
depends on BOARD_SUPERMICRO_X6DHR_IG
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 4
|
||||
depends on BOARD_SUPERMICRO_X6DHR_IG
|
||||
|
||||
config USE_INIT
|
||||
bool
|
||||
default n
|
||||
depends on BOARD_SUPERMICRO_X6DHR_IG
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 15
|
||||
depends on BOARD_SUPERMICRO_X6DHR_IG
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
ROMCCFLAGS=-mcpu=p4 -O2
|
||||
|
||||
include $(src)/mainboard/Makefile.romccboard.inc
|
||||
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
config BOARD_SUPERMICRO_X6DHR_IG2
|
||||
bool "X6DHR-IG"
|
||||
select ARCH_X86
|
||||
select CPU_INTEL_SOCKET_MPGA604
|
||||
select NORTHBRIDGE_INTEL_E7520
|
||||
select SOUTHBRIDGE_INTEL_I82801ER
|
||||
select SOUTHBRIDGE_INTEL_PXHD
|
||||
select SUPERIO_WINBOND_W83627HF
|
||||
select PIRQ_TABLE
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default supermicro/x6dhr_ig2
|
||||
depends on BOARD_SUPERMICRO_X6DHR_IG2
|
||||
|
||||
config LB_CKS_RANGE_END
|
||||
int
|
||||
default 122
|
||||
depends on BOARD_SUPERMICRO_X6DHR_IG2
|
||||
|
||||
config LB_CKS_LOC
|
||||
int
|
||||
default 123
|
||||
depends on BOARD_SUPERMICRO_X6DHR_IG2
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "X6DHR_IG2"
|
||||
depends on BOARD_SUPERMICRO_X6DHR_IG2
|
||||
|
||||
config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
|
||||
hex
|
||||
default 0x15d9
|
||||
depends on BOARD_SUPERMICRO_X6DHR_IG2
|
||||
|
||||
config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
|
||||
hex
|
||||
default 0x6780
|
||||
depends on BOARD_SUPERMICRO_X6DHR_IG2
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 4
|
||||
depends on BOARD_SUPERMICRO_X6DHR_IG2
|
||||
|
||||
config USE_INIT
|
||||
bool
|
||||
default n
|
||||
depends on BOARD_SUPERMICRO_X6DHR_IG2
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 15
|
||||
depends on BOARD_SUPERMICRO_X6DHR_IG2
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
ROMCCFLAGS=-mcpu=p4 -O2
|
||||
|
||||
include $(src)/mainboard/Makefile.romccboard.inc
|
||||
|
||||
Loading…
Reference in New Issue