From 01025d3ae78e02192d389f22abd36747e3d8c63b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 12 Jul 2023 13:22:09 +0200 Subject: [PATCH] soc/intel/alderlake: Depend RPL-guarded FSP UPDs on FSP_USE_REPO MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Only the headers on Intel FSP repository have the CnviWifiCore present. Options guarded for RPL like: DisableDynamicTccoldHandshake or EnableFastVmode and IccLimit is also supported by all public FSPs (except ADL-N for the handshake). Options like LowerBasicMemTestSize and DisableSagvReorder have to be guarded when FSP_USE_REPO is not selected, as publci FSPs do not have these options. Use FSP_USE_REPO instead of/in addition to SOC_INTEL_RAPTORLAKE as dependency on the guarded UPDs to make them available for FSPs that support them as well. Also prioritize the headers from FSP repo over vendorcode headers if FSP_USE_REPO is selected. Change-Id: Id5a2da463a74f4ac80dcb407a39fc45b0b6a10a8 Signed-off-by: Michał Żygowski Reviewed-on: https://review.coreboot.org/c/coreboot/+/76418 Tested-by: build bot (Jenkins) Reviewed-by: Michał Kopeć --- src/soc/intel/alderlake/Kconfig | 6 +++--- src/soc/intel/alderlake/fsp_params.c | 9 +++------ src/soc/intel/alderlake/include/soc/vr_config.h | 2 +- src/soc/intel/alderlake/romstage/fsp_params.c | 5 +++-- src/soc/intel/alderlake/vr_config.c | 2 +- 5 files changed, 11 insertions(+), 13 deletions(-) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 782ce22f40..3e8f767dbc 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -397,13 +397,13 @@ config FSP_TYPE_IOT config FSP_HEADER_PATH string "Location of FSP headers" - default "src/vendorcode/intel/fsp/fsp2_0/alderlake_n/" if SOC_INTEL_ALDERLAKE_PCH_N - default "src/vendorcode/intel/fsp/fsp2_0/raptorlake/" if SOC_INTEL_RAPTORLAKE + default "src/vendorcode/intel/fsp/fsp2_0/alderlake_n/" if SOC_INTEL_ALDERLAKE_PCH_N && !FSP_USE_REPO + default "src/vendorcode/intel/fsp/fsp2_0/raptorlake/" if SOC_INTEL_RAPTORLAKE && !FSP_USE_REPO default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P && FSP_TYPE_IOT default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeS/Include/" if SOC_INTEL_ALDERLAKE_PCH_S && FSP_TYPE_IOT default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeS/Include/" if SOC_INTEL_ALDERLAKE_PCH_S - default "src/vendorcode/intel/fsp/fsp2_0/alderlake/" + default "src/vendorcode/intel/fsp/fsp2_0/alderlake/" if !FSP_USE_REPO config FSP_FD_PATH string diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 13abd6f975..2260259753 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -818,11 +818,9 @@ static void fill_fsps_cnvi_params(FSP_S_CONFIG *s_cfg, const struct soc_intel_alderlake_config *config) { /* CNVi */ -#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_P) || CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) -#if !CONFIG(SOC_INTEL_RAPTORLAKE) - /* This option is only available in public FSP headers of ADL-P and ADL-S */ +#if CONFIG(FSP_USE_REPO) + /* This option is only available in public FSP headers on FSP repo */ s_cfg->CnviWifiCore = is_devfn_enabled(PCH_DEVFN_CNVI_WIFI); -#endif #endif s_cfg->CnviMode = is_devfn_enabled(PCH_DEVFN_CNVI_WIFI); s_cfg->CnviBtCore = config->cnvi_bt_core; @@ -1032,8 +1030,7 @@ static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg, s_cfg->C1e = 0; else s_cfg->C1e = 1; - -#if CONFIG(SOC_INTEL_RAPTORLAKE) +#if CONFIG(SOC_INTEL_RAPTORLAKE) && !CONFIG(FSP_USE_REPO) s_cfg->EnableHwpScalabilityTracking = config->enable_hwp_scalability_tracking; #endif } diff --git a/src/soc/intel/alderlake/include/soc/vr_config.h b/src/soc/intel/alderlake/include/soc/vr_config.h index 41c2f6b55e..f43daf2391 100644 --- a/src/soc/intel/alderlake/include/soc/vr_config.h +++ b/src/soc/intel/alderlake/include/soc/vr_config.h @@ -8,7 +8,7 @@ #include struct vr_config { -#if CONFIG(SOC_INTEL_RAPTORLAKE) +#if CONFIG(SOC_INTEL_RAPTORLAKE) || CONFIG(FSP_USE_REPO) /* * When enabled, this feature makes the SoC throttle when the power * consumption exceeds the I_TRIP threshold. diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 9bab919fb6..59cd8ff1b8 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -158,7 +158,7 @@ static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg, m_cfg->DdrFreqLimit = config->max_dram_speed_mts; m_cfg->DdrSpeedControl = 1; } -#if CONFIG(SOC_INTEL_RAPTORLAKE) +#if CONFIG(SOC_INTEL_RAPTORLAKE) && !CONFIG(FSP_USE_REPO) m_cfg->LowerBasicMemTestSize = config->lower_basic_mem_test_size; m_cfg->DisableSagvReorder = config->disable_sagv_reorder; #endif @@ -272,7 +272,8 @@ static void fill_fspm_tcss_params(FSP_M_CONFIG *m_cfg, m_cfg->TcssDma0En = is_devfn_enabled(SA_DEVFN_TCSS_DMA0); m_cfg->TcssDma1En = is_devfn_enabled(SA_DEVFN_TCSS_DMA1); -#if CONFIG(SOC_INTEL_RAPTORLAKE) +#if (CONFIG(SOC_INTEL_RAPTORLAKE) && !CONFIG(FSP_USE_REPO)) || \ + (!CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) && CONFIG(FSP_USE_REPO)) m_cfg->DisableDynamicTccoldHandshake = config->disable_dynamic_tccold_handshake; #endif diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c index cec2dd385f..3467bdd139 100644 --- a/src/soc/intel/alderlake/vr_config.c +++ b/src/soc/intel/alderlake/vr_config.c @@ -353,7 +353,7 @@ static const struct vr_lookup vr_config_tdc_currentlimit[] = { static void fill_vr_fast_vmode(FSP_S_CONFIG *s_cfg, int domain, const struct vr_config *chip_cfg) { -#if CONFIG(SOC_INTEL_RAPTORLAKE) +#if CONFIG(SOC_INTEL_RAPTORLAKE) || CONFIG(FSP_USE_REPO) s_cfg->EnableFastVmode[domain] = chip_cfg->enable_fast_vmode; if (s_cfg->EnableFastVmode[domain]) s_cfg->IccLimit[domain] = chip_cfg->fast_vmode_i_trip;