AMD: Uniformly define MSRs for TOP_MEM and TOP_MEM2
Make the build tolerate re-definitions. Change-Id: Ia7505837c70b1f749262508b26576e95c7865576 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8609 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
parent
c13fc15a45
commit
0127c6c808
|
@ -468,8 +468,8 @@ all_mtrr_msrs:
|
||||||
.long IORRMask_MSR(1)
|
.long IORRMask_MSR(1)
|
||||||
|
|
||||||
/* Top of memory MTRR MSRs */
|
/* Top of memory MTRR MSRs */
|
||||||
.long TOP_MEM_MSR
|
.long TOP_MEM
|
||||||
.long TOP_MEM2_MSR
|
.long TOP_MEM2
|
||||||
|
|
||||||
.long 0x000 /* NULL, end of table */
|
.long 0x000 /* NULL, end of table */
|
||||||
|
|
||||||
|
|
|
@ -25,13 +25,12 @@
|
||||||
#define IORRBase_MSR(reg) (0xC0010016 + 2 * (reg))
|
#define IORRBase_MSR(reg) (0xC0010016 + 2 * (reg))
|
||||||
#define IORRMask_MSR(reg) (0xC0010016 + 2 * (reg) + 1)
|
#define IORRMask_MSR(reg) (0xC0010016 + 2 * (reg) + 1)
|
||||||
|
|
||||||
#define TOP_MEM_MSR 0xC001001A
|
#if defined(__ASSEMBLER__)
|
||||||
#define TOP_MEM2_MSR 0xC001001D
|
#define TOP_MEM 0xC001001A
|
||||||
#ifndef TOP_MEM
|
#define TOP_MEM2 0xC001001D
|
||||||
#define TOP_MEM TOP_MEM_MSR
|
#else
|
||||||
#endif
|
#define TOP_MEM 0xC001001Aul
|
||||||
#ifndef TOP_MEM2
|
#define TOP_MEM2 0xC001001Dul
|
||||||
#define TOP_MEM2 TOP_MEM2_MSR
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define TOP_MEM_MASK 0x007fffff
|
#define TOP_MEM_MASK 0x007fffff
|
||||||
|
|
|
@ -1012,12 +1012,8 @@ typedef enum {
|
||||||
|
|
||||||
///< CPU MSR Register definitions ------------------------------------------
|
///< CPU MSR Register definitions ------------------------------------------
|
||||||
#define SYS_CFG 0xC0010010
|
#define SYS_CFG 0xC0010010
|
||||||
#ifndef TOP_MEM
|
#define TOP_MEM 0xC001001Aul
|
||||||
#define TOP_MEM 0xC001001A
|
#define TOP_MEM2 0xC001001Dul
|
||||||
#endif
|
|
||||||
#ifndef TOP_MEM2
|
|
||||||
#define TOP_MEM2 0xC001001D
|
|
||||||
#endif
|
|
||||||
#define HWCR 0xC0010015
|
#define HWCR 0xC0010015
|
||||||
#define NB_CFG 0xC001001F
|
#define NB_CFG 0xC001001F
|
||||||
|
|
||||||
|
|
|
@ -92,7 +92,7 @@
|
||||||
#define NorthbridgeCapabilities 0xE8
|
#define NorthbridgeCapabilities 0xE8
|
||||||
#define DRAMBase0 0x40
|
#define DRAMBase0 0x40
|
||||||
#define MMIOBase0 0x80
|
#define MMIOBase0 0x80
|
||||||
#define TOP_MEM 0xC001001A
|
#define TOP_MEM 0xC001001Aul
|
||||||
#define LOW_NODE_DEVICEID 24
|
#define LOW_NODE_DEVICEID 24
|
||||||
#define LOW_APICID 0
|
#define LOW_APICID 0
|
||||||
|
|
||||||
|
|
|
@ -1279,12 +1279,8 @@ typedef enum {
|
||||||
|
|
||||||
///< CPU MSR Register definitions ------------------------------------------
|
///< CPU MSR Register definitions ------------------------------------------
|
||||||
#define SYS_CFG 0xC0010010
|
#define SYS_CFG 0xC0010010
|
||||||
#ifndef TOP_MEM
|
#define TOP_MEM 0xC001001Aul
|
||||||
#define TOP_MEM 0xC001001A
|
#define TOP_MEM2 0xC001001Dul
|
||||||
#endif
|
|
||||||
#ifndef TOP_MEM2
|
|
||||||
#define TOP_MEM2 0xC001001D
|
|
||||||
#endif
|
|
||||||
#define HWCR 0xC0010015
|
#define HWCR 0xC0010015
|
||||||
#define NB_CFG 0xC001001F
|
#define NB_CFG 0xC001001F
|
||||||
|
|
||||||
|
|
|
@ -101,7 +101,7 @@ AGESA_FORWARD_DECLARATION (PROC_FAMILY_TABLE);
|
||||||
#define NorthbridgeCapabilities 0xE8
|
#define NorthbridgeCapabilities 0xE8
|
||||||
#define DRAMBase0 0x40
|
#define DRAMBase0 0x40
|
||||||
#define MMIOBase0 0x80
|
#define MMIOBase0 0x80
|
||||||
#define TOP_MEM 0xC001001A
|
#define TOP_MEM 0xC001001Aul
|
||||||
#define LOW_NODE_DEVICEID 24
|
#define LOW_NODE_DEVICEID 24
|
||||||
#define LOW_APICID 0
|
#define LOW_APICID 0
|
||||||
|
|
||||||
|
|
|
@ -1129,12 +1129,8 @@ typedef enum {
|
||||||
|
|
||||||
///< CPU MSR Register definitions ------------------------------------------
|
///< CPU MSR Register definitions ------------------------------------------
|
||||||
#define SYS_CFG 0xC0010010
|
#define SYS_CFG 0xC0010010
|
||||||
#ifndef TOP_MEM
|
#define TOP_MEM 0xC001001Aul
|
||||||
#define TOP_MEM 0xC001001A
|
#define TOP_MEM2 0xC001001Dul
|
||||||
#endif
|
|
||||||
#ifndef TOP_MEM2
|
|
||||||
#define TOP_MEM2 0xC001001D
|
|
||||||
#endif
|
|
||||||
#define HWCR 0xC0010015
|
#define HWCR 0xC0010015
|
||||||
#define NB_CFG 0xC001001F
|
#define NB_CFG 0xC001001F
|
||||||
|
|
||||||
|
|
|
@ -98,7 +98,7 @@
|
||||||
#define NorthbridgeCapabilities 0xE8
|
#define NorthbridgeCapabilities 0xE8
|
||||||
#define DRAMBase0 0x40
|
#define DRAMBase0 0x40
|
||||||
#define MMIOBase0 0x80
|
#define MMIOBase0 0x80
|
||||||
#define TOP_MEM 0xC001001A
|
#define TOP_MEM 0xC001001Aul
|
||||||
#define LOW_NODE_DEVICEID 24
|
#define LOW_NODE_DEVICEID 24
|
||||||
#define LOW_APICID 0
|
#define LOW_APICID 0
|
||||||
|
|
||||||
|
|
|
@ -1418,14 +1418,8 @@ typedef enum {
|
||||||
|
|
||||||
///< CPU MSR Register definitions ------------------------------------------
|
///< CPU MSR Register definitions ------------------------------------------
|
||||||
#define SYS_CFG 0xC0010010
|
#define SYS_CFG 0xC0010010
|
||||||
//#define TOP_MEM 0xC001001A
|
#define TOP_MEM 0xC001001Aul
|
||||||
//#define TOP_MEM2 0xC001001D
|
#define TOP_MEM2 0xC001001Dul
|
||||||
#ifndef TOP_MEM
|
|
||||||
#define TOP_MEM 0xC001001A
|
|
||||||
#endif
|
|
||||||
#ifndef TOP_MEM2
|
|
||||||
#define TOP_MEM2 0xC001001D
|
|
||||||
#endif
|
|
||||||
#define HWCR 0xC0010015
|
#define HWCR 0xC0010015
|
||||||
#define NB_CFG 0xC001001F
|
#define NB_CFG 0xC001001F
|
||||||
|
|
||||||
|
|
|
@ -116,7 +116,7 @@ CpuLateInitApTask (
|
||||||
#define NorthbridgeCapabilities 0xE8
|
#define NorthbridgeCapabilities 0xE8
|
||||||
#define DRAMBase0 0x40
|
#define DRAMBase0 0x40
|
||||||
#define MMIOBase0 0x80
|
#define MMIOBase0 0x80
|
||||||
#define TOP_MEM 0xC001001A
|
#define TOP_MEM 0xC001001Aul
|
||||||
#define LOW_NODE_DEVICEID 24
|
#define LOW_NODE_DEVICEID 24
|
||||||
#define LOW_APICID 0
|
#define LOW_APICID 0
|
||||||
|
|
||||||
|
|
|
@ -1590,12 +1590,8 @@ typedef enum {
|
||||||
|
|
||||||
///< CPU MSR Register definitions ------------------------------------------
|
///< CPU MSR Register definitions ------------------------------------------
|
||||||
#define SYS_CFG 0xC0010010ul
|
#define SYS_CFG 0xC0010010ul
|
||||||
#ifndef TOP_MEM
|
|
||||||
#define TOP_MEM 0xC001001Aul
|
#define TOP_MEM 0xC001001Aul
|
||||||
#endif
|
|
||||||
#ifndef TOP_MEM2
|
|
||||||
#define TOP_MEM2 0xC001001Dul
|
#define TOP_MEM2 0xC001001Dul
|
||||||
#endif
|
|
||||||
#define HWCR 0xC0010015ul
|
#define HWCR 0xC0010015ul
|
||||||
#define NB_CFG 0xC001001Ful
|
#define NB_CFG 0xC001001Ful
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue