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AMD: Uniformly define MSRs for TOP_MEM and TOP_MEM2 

Make the build tolerate re-definitions.

Change-Id: Ia7505837c70b1f749262508b26576e95c7865576
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8609
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Kyösti Mälkki 2015-03-05 14:35:04 +02:00
parent c13fc15a45
commit 0127c6c808
11 changed files with 20 additions and 43 deletions
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4
src/cpu/amd/car/cache_as_ram.inc
View File

@ -468,8 +468,8 @@ all_mtrr_msrs:
.long IORRMask_MSR(1)
/* Top of memory MTRR MSRs */
.long TOP_MEM_MSR
.long TOP_MEM2_MSR
.long TOP_MEM
.long TOP_MEM2
.long 0x000 /* NULL, end of table */

13
src/include/cpu/amd/mtrr.h
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@ -25,13 +25,12 @@
#define IORRBase_MSR(reg) (0xC0010016 + 2 * (reg))
#define IORRMask_MSR(reg) (0xC0010016 + 2 * (reg) + 1)
#define TOP_MEM_MSR 0xC001001A
#define TOP_MEM2_MSR 0xC001001D
#ifndef TOP_MEM
#define TOP_MEM TOP_MEM_MSR
#endif
#ifndef TOP_MEM2
#define TOP_MEM2 TOP_MEM2_MSR
#if defined(__ASSEMBLER__)
#define TOP_MEM 0xC001001A
#define TOP_MEM2 0xC001001D
#else
#define TOP_MEM 0xC001001Aul
#define TOP_MEM2 0xC001001Dul
#endif
#define TOP_MEM_MASK 0x007fffff

8
src/vendorcode/amd/agesa/f10/AGESA.h
View File

@ -1012,12 +1012,8 @@ typedef enum {
///< CPU MSR Register definitions ------------------------------------------
#define SYS_CFG 0xC0010010
#ifndef TOP_MEM
#define TOP_MEM 0xC001001A
#endif
#ifndef TOP_MEM2
#define TOP_MEM2 0xC001001D
#endif
#define TOP_MEM 0xC001001Aul
#define TOP_MEM2 0xC001001Dul
#define HWCR 0xC0010015
#define NB_CFG 0xC001001F

2
src/vendorcode/amd/agesa/f10/Proc/CPU/cpuLateInit.h
View File

@ -92,7 +92,7 @@
#define NorthbridgeCapabilities 0xE8
#define DRAMBase0 0x40
#define MMIOBase0 0x80
#define TOP_MEM 0xC001001A
#define TOP_MEM 0xC001001Aul
#define LOW_NODE_DEVICEID 24
#define LOW_APICID 0

8
src/vendorcode/amd/agesa/f12/AGESA.h
View File

@ -1279,12 +1279,8 @@ typedef enum {
///< CPU MSR Register definitions ------------------------------------------
#define SYS_CFG 0xC0010010
#ifndef TOP_MEM
#define TOP_MEM 0xC001001A
#endif
#ifndef TOP_MEM2
#define TOP_MEM2 0xC001001D
#endif
#define TOP_MEM 0xC001001Aul
#define TOP_MEM2 0xC001001Dul
#define HWCR 0xC0010015
#define NB_CFG 0xC001001F

2
src/vendorcode/amd/agesa/f12/Proc/CPU/cpuLateInit.h
View File

@ -101,7 +101,7 @@ AGESA_FORWARD_DECLARATION (PROC_FAMILY_TABLE);
#define NorthbridgeCapabilities 0xE8
#define DRAMBase0 0x40
#define MMIOBase0 0x80
#define TOP_MEM 0xC001001A
#define TOP_MEM 0xC001001Aul
#define LOW_NODE_DEVICEID 24
#define LOW_APICID 0

8
src/vendorcode/amd/agesa/f14/AGESA.h
View File

@ -1129,12 +1129,8 @@ typedef enum {
///< CPU MSR Register definitions ------------------------------------------
#define SYS_CFG 0xC0010010
#ifndef TOP_MEM
#define TOP_MEM 0xC001001A
#endif
#ifndef TOP_MEM2
#define TOP_MEM2 0xC001001D
#endif
#define TOP_MEM 0xC001001Aul
#define TOP_MEM2 0xC001001Dul
#define HWCR 0xC0010015
#define NB_CFG 0xC001001F

2
src/vendorcode/amd/agesa/f14/Proc/CPU/cpuLateInit.h
View File

@ -98,7 +98,7 @@
#define NorthbridgeCapabilities 0xE8
#define DRAMBase0 0x40
#define MMIOBase0 0x80
#define TOP_MEM 0xC001001A
#define TOP_MEM 0xC001001Aul
#define LOW_NODE_DEVICEID 24
#define LOW_APICID 0

10
src/vendorcode/amd/agesa/f15/AGESA.h
View File

@ -1418,14 +1418,8 @@ typedef enum {
///< CPU MSR Register definitions ------------------------------------------
#define SYS_CFG 0xC0010010
//#define TOP_MEM 0xC001001A
//#define TOP_MEM2 0xC001001D
#ifndef TOP_MEM
#define TOP_MEM 0xC001001A
#endif
#ifndef TOP_MEM2
#define TOP_MEM2 0xC001001D
#endif
#define TOP_MEM 0xC001001Aul
#define TOP_MEM2 0xC001001Dul
#define HWCR 0xC0010015
#define NB_CFG 0xC001001F

2
src/vendorcode/amd/agesa/f15/Proc/CPU/cpuLateInit.h
View File

@ -116,7 +116,7 @@ CpuLateInitApTask (
#define NorthbridgeCapabilities 0xE8
#define DRAMBase0 0x40
#define MMIOBase0 0x80
#define TOP_MEM 0xC001001A
#define TOP_MEM 0xC001001Aul
#define LOW_NODE_DEVICEID 24
#define LOW_APICID 0

4
src/vendorcode/amd/agesa/f16kb/AGESA.h
View File

@ -1590,12 +1590,8 @@ typedef enum {
///< CPU MSR Register definitions ------------------------------------------
#define SYS_CFG 0xC0010010ul
#ifndef TOP_MEM
#define TOP_MEM 0xC001001Aul
#endif
#ifndef TOP_MEM2
#define TOP_MEM2 0xC001001Dul
#endif
#define HWCR 0xC0010015ul
#define NB_CFG 0xC001001Ful