Combine Broadwell Chromeboxes using variant board scheme
Combine existing boards google/guado, rikku, and tidus using their common reference board google/jecht as a base. Additional changes besides simple consolidation include: - simplify power LED functions - simplify HDA verb definitions using azelia macros - use common SoC functions to generate FADT table - correct FADT table header version - remove unused haswell_pci_irqs.asl - remove unused header includes (various) - set sane default fan speed (0x4d) for all variants Variant setup modeled after google/beltino Change-Id: I77a2dffe9601734916a33fd04ead98016ad0bc4b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17913 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Matt DeVillier
Martin Roth
parent
6390e525fc
commit
0148fcb4e1
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@ -1,59 +0,0 @@
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if BOARD_GOOGLE_GUADO
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select SOC_INTEL_BROADWELL
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select BOARD_ROMSIZE_KB_8192
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select SUPERIO_ITE_IT8772F
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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select HAVE_ACPI_RESUME
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select HAVE_SMI_HANDLER
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_HAS_LPC_TPM
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config CHROMEOS
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select CHROMEOS_RAMOOPS_DYNAMIC
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select PHYSICAL_REC_SWITCH
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select VBOOT_VBNV_CMOS
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select VIRTUAL_DEV_SWITCH
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config MAINBOARD_DIR
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string
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default google/guado
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config MAINBOARD_PART_NUMBER
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string
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default "Guado"
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config IRQ_SLOT_COUNT
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int
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default 18
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config MAX_CPUS
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int
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default 8
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config VGA_BIOS_FILE
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string
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default "pci8086,0166.rom"
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config HAVE_IFD_BIN
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bool
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default n
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config HAVE_ME_BIN
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bool
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default n
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config MAINBOARD_FAMILY
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string
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depends on GENERATE_SMBIOS_TABLES
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default "Google_Guado"
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config GBB_HWID
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string
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depends on CHROMEOS
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default "GUADO TEST A-A 7416"
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endif
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@ -1,2 +0,0 @@
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config BOARD_GOOGLE_GUADO
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bool "Guado"
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@ -1,24 +0,0 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2014 Google Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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subdirs-y += spd
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romstage-$(CONFIG_CHROMEOS) += chromeos.c
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ramstage-$(CONFIG_CHROMEOS) += chromeos.c
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ramstage-y += lan.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
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romstage-y += pei_data.c
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ramstage-y += pei_data.c
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@ -1,82 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* This is board specific information: IRQ routing for IvyBridge */
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// PCI Interrupt Routing
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Method(_PRT)
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{
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If (PICM) {
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Return (Package() {
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// Onboard graphics (IGD) 0:2.0
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Package() { 0x0002ffff, 0, 0, 16 },
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// Mini-HD Audio 0:3.0
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Package() { 0x0003ffff, 0, 0, 16 },
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// High Definition Audio 0:1b.0
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Package() { 0x001bffff, 0, 0, 22 },
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// PCIe Root Ports 0:1c.x
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Package() { 0x001cffff, 0, 0, 16 },
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Package() { 0x001cffff, 1, 0, 17 },
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Package() { 0x001cffff, 2, 0, 18 },
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Package() { 0x001cffff, 3, 0, 19 },
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// EHCI 0:1d.0
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Package() { 0x001dffff, 0, 0, 19 },
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// XHCI 0:14.0
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Package() { 0x0014ffff, 0, 0, 18 },
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// LPC devices 0:1f.0
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Package() { 0x001fffff, 0, 0, 22 },
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Package() { 0x001fffff, 1, 0, 18 },
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Package() { 0x001fffff, 2, 0, 17 },
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Package() { 0x001fffff, 3, 0, 16 },
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// Serial IO 0:15.0
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Package() { 0x0015ffff, 0, 0, 20 },
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Package() { 0x0015ffff, 1, 0, 21 },
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Package() { 0x0015ffff, 2, 0, 21 },
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Package() { 0x0015ffff, 3, 0, 21 },
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// SDIO 0:17.0
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Package() { 0x0017ffff, 0, 0, 23 },
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})
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} Else {
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Return (Package() {
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// Onboard graphics (IGD) 0:2.0
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Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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// Mini-HD Audio 0:3.0
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Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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// High Definition Audio 0:1b.0
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Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
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// PCIe Root Ports 0:1c.x
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Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
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Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
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Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
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// EHCI 0:1d.0
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Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
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// XHCI 0:14.0
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Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
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// LPC device 0:1f.0
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Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
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Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
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Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
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Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
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// Serial IO 0:15.0
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Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
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Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
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Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 },
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Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 },
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// SDIO 0:17.0
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Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
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})
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}
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}
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@ -1,69 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <mainboard/google/guado/onboard.h>
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Scope (\_SB)
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{
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Device (PWRB)
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{
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Name(_HID, EisaId("PNP0C0C"))
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}
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}
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/*
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* LAN connected to Root Port 3, becomes Root Port 1 after coalesce
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*/
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Scope (\_SB.PCI0.RP01)
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{
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Device (ETH0)
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{
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Name (_ADR, 0x00000000)
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Name (_PRW, Package() { GUADO_NIC_WAKE_GPIO, 3 })
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Method (_DSW, 3, NotSerialized)
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{
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Store (GUADO_NIC_WAKE_GPIO, Local0)
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If (LEqual (Arg0, 1)) {
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// Enable GPIO as wake source
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\_SB.PCI0.LPCB.GPIO.GWAK (Local0)
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}
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}
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}
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}
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/*
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* WLAN connected to Root Port 4, becomes Root Port 2 after coalesce
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*/
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Scope (\_SB.PCI0.RP02)
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{
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Device (WLAN)
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{
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Name (_ADR, 0x00000000)
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Name (_PRW, Package() { GUADO_WLAN_WAKE_GPIO, 3 })
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Method (_DSW, 3, NotSerialized)
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{
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Store (GUADO_WLAN_WAKE_GPIO, Local0)
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If (LEqual (Arg0, 1)) {
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// Enable GPIO as wake source
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\_SB.PCI0.LPCB.GPIO.GWAK (Local0)
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}
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}
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}
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}
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@ -1,71 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* The APM port can be used for generating software SMIs */
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OperationRegion (APMP, SystemIO, 0xb2, 2)
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Field (APMP, ByteAcc, NoLock, Preserve)
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{
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APMC, 8, // APM command
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APMS, 8 // APM status
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}
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/* Port 80 POST */
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OperationRegion (POST, SystemIO, 0x80, 1)
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Field (POST, ByteAcc, Lock, Preserve)
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{
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DBG0, 8
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}
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/* SMI I/O Trap */
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Method(TRAP, 1, Serialized)
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{
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Store (Arg0, SMIF) // SMI Function
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Store (0, TRP0) // Generate trap
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Return (SMIF) // Return value of SMI handler
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}
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/* The _PIC method is called by the OS to choose between interrupt
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* routing via the i8259 interrupt controller or the APIC.
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*
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* _PIC is called with a parameter of 0 for i8259 configuration and
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* with a parameter of 1 for Local Apic/IOAPIC configuration.
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*/
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Method(_PIC, 1)
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{
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// Remember the OS' IRQ routing choice.
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Store(Arg0, PICM)
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}
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/* The _PTS method (Prepare To Sleep) is called before the OS is
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* entering a sleep state. The sleep state number is passed in Arg0
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*/
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Method(_PTS,1)
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{
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}
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/* The _WAK method is called on system wakeup */
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|
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Method(_WAK,1)
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{
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/* Initialize thermal defaults */
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\_TZ.THRM._INI ()
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Return(Package(){0,0})
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}
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@ -1,31 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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||||
* Copyright (C) 2012 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
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/* Values should match those defined in devicetree.cb */
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#undef SIO_ENABLE_FDC0 // pnp 2e.0: Disable Floppy Controller
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#undef SIO_ENABLE_INFR // pnp 2e.a: Disable Consumer IR
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#undef SIO_ENABLE_PS2K // pnp 2e.5: Disable PS/2 Keyboard
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#undef SIO_ENABLE_PS2M // pnp 2e.6: Disable PS/2 Mouse
|
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#define SIO_ENABLE_COM1 // pnp 2e.1: Enable Serial Port 1
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#define SIO_ENABLE_ENVC // pnp 2e.4: Enable Environmental Controller
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#define SIO_ENVC_IO0 0x700 // pnp 2e.4: io 0x60
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#define SIO_ENVC_IO1 0x710 // pnp 2e.4: io 0x62
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#define SIO_ENABLE_GPIO // pnp 2e.7: Enable GPIO
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#define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60
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#define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60
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|
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#include "superio/ite/it8772f/acpi/superio.asl"
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|
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@ -1,38 +0,0 @@
|
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/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
// Brightness write
|
||||
Method (BRTW, 1, Serialized)
|
||||
{
|
||||
// TODO
|
||||
}
|
||||
|
||||
// Hot Key Display Switch
|
||||
Method (HKDS, 1, Serialized)
|
||||
{
|
||||
// TODO
|
||||
}
|
||||
|
||||
// Lid Switch Display Switch
|
||||
Method (LSDS, 1, Serialized)
|
||||
{
|
||||
// TODO
|
||||
}
|
||||
|
||||
// Brightness Notification
|
||||
Method(BRTN,1,Serialized)
|
||||
{
|
||||
// TODO (no displays defined yet)
|
||||
}
|
||||
|
|
@ -1,65 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <types.h>
|
||||
#include <string.h>
|
||||
#include <cbmem.h>
|
||||
#include <console/console.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <arch/acpigen.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <soc/acpi.h>
|
||||
#include <soc/nvs.h>
|
||||
#include "thermal.h"
|
||||
|
||||
|
||||
static void acpi_update_thermal_table(global_nvs_t *gnvs)
|
||||
{
|
||||
gnvs->tmps = TEMPERATURE_SENSOR_ID;
|
||||
|
||||
gnvs->tcrt = CRITICAL_TEMPERATURE;
|
||||
gnvs->tpsv = PASSIVE_TEMPERATURE;
|
||||
gnvs->tmax = MAX_TEMPERATURE;
|
||||
gnvs->flvl = 1;
|
||||
}
|
||||
|
||||
void acpi_create_gnvs(global_nvs_t *gnvs)
|
||||
{
|
||||
acpi_init_gnvs(gnvs);
|
||||
|
||||
/* Enable USB ports in S3 */
|
||||
gnvs->s3u0 = 1;
|
||||
|
||||
/* Disable USB ports in S5 */
|
||||
gnvs->s5u0 = 0;
|
||||
|
||||
acpi_update_thermal_table(gnvs);
|
||||
}
|
||||
|
||||
unsigned long acpi_fill_madt(unsigned long current)
|
||||
{
|
||||
/* Local APICs */
|
||||
current = acpi_create_madt_lapics(current);
|
||||
|
||||
/* IOAPIC */
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
|
||||
2, IO_APIC_ADDR, 0);
|
||||
|
||||
return acpi_madt_irq_overrides(current);
|
||||
}
|
||||
|
|
@ -1,7 +0,0 @@
|
|||
Vendor name: Asus
|
||||
Board name: Chromebox2
|
||||
Category: half
|
||||
ROM package: SOIC-8
|
||||
ROM protocol: SPI
|
||||
ROM socketed: n
|
||||
Flashrom support: y
|
||||
|
|
@ -1,105 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <console/console.h>
|
||||
#include <vendorcode/google/chromeos/chromeos.h>
|
||||
#include <ec/google/chromeec/ec.h>
|
||||
#include <soc/gpio.h>
|
||||
#include <soc/sata.h>
|
||||
|
||||
#define GPIO_SPI_WP 58
|
||||
#define GPIO_REC_MODE 12
|
||||
|
||||
#define FLAG_SPI_WP 0
|
||||
#define FLAG_REC_MODE 1
|
||||
#define FLAG_DEV_MODE 2
|
||||
|
||||
#ifndef __PRE_RAM__
|
||||
#include <boot/coreboot_tables.h>
|
||||
|
||||
void fill_lb_gpios(struct lb_gpios *gpios)
|
||||
{
|
||||
struct lb_gpio chromeos_gpios[] = {
|
||||
{GPIO_SPI_WP, ACTIVE_HIGH, 0, "write protect"},
|
||||
{GPIO_REC_MODE, ACTIVE_LOW,
|
||||
get_recovery_mode_switch(), "recovery"},
|
||||
{-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"},
|
||||
{-1, ACTIVE_HIGH, 1, "lid"},
|
||||
{-1, ACTIVE_HIGH, 0, "power"},
|
||||
{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
|
||||
};
|
||||
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
|
||||
}
|
||||
#endif
|
||||
|
||||
int get_write_protect_state(void)
|
||||
{
|
||||
device_t dev;
|
||||
#ifdef __PRE_RAM__
|
||||
dev = PCI_DEV(0, 0x1f, 2);
|
||||
#else
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
|
||||
#endif
|
||||
return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;
|
||||
}
|
||||
|
||||
int get_developer_mode_switch(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int get_recovery_mode_switch(void)
|
||||
{
|
||||
device_t dev;
|
||||
#ifdef __PRE_RAM__
|
||||
dev = PCI_DEV(0, 0x1f, 2);
|
||||
#else
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
|
||||
#endif
|
||||
return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;
|
||||
}
|
||||
|
||||
#ifdef __PRE_RAM__
|
||||
void save_chromeos_gpios(void)
|
||||
{
|
||||
u32 flags = 0;
|
||||
|
||||
/* Write Protect: GPIO58 = GPIO_SPI_WP, active high */
|
||||
if (get_gpio(GPIO_SPI_WP))
|
||||
flags |= (1 << FLAG_SPI_WP);
|
||||
|
||||
/* Recovery: GPIO12 = RECOVERY_L, active low */
|
||||
if (!get_gpio(GPIO_REC_MODE))
|
||||
flags |= (1 << FLAG_REC_MODE);
|
||||
|
||||
/* Developer: Virtual */
|
||||
|
||||
pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags);
|
||||
}
|
||||
#endif
|
||||
|
||||
static const struct cros_gpio cros_gpios[] = {
|
||||
CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME),
|
||||
CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
|
||||
};
|
||||
|
||||
void mainboard_chromeos_acpi_generate(void)
|
||||
{
|
||||
chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
|
||||
}
|
||||
|
|
@ -1,38 +0,0 @@
|
|||
FLASH@0xff800000 0x800000 {
|
||||
SI_ALL@0x0 0x200000 {
|
||||
SI_DESC@0x0 0x1000
|
||||
SI_ME@0x1000 0x1ff000
|
||||
}
|
||||
SI_BIOS@0x200000 0x600000 {
|
||||
RW_SECTION_A@0x0 0xf0000 {
|
||||
VBLOCK_A@0x0 0x10000
|
||||
FW_MAIN_A(CBFS)@0x10000 0xdffc0
|
||||
RW_FWID_A@0xeffc0 0x40
|
||||
}
|
||||
RW_SECTION_B@0xf0000 0xf0000 {
|
||||
VBLOCK_B@0x0 0x10000
|
||||
FW_MAIN_B(CBFS)@0x10000 0xdffc0
|
||||
RW_FWID_B@0xeffc0 0x40
|
||||
}
|
||||
RW_MRC_CACHE@0x1e0000 0x10000
|
||||
RW_ELOG@0x1f0000 0x4000
|
||||
RW_SHARED@0x1f4000 0x4000 {
|
||||
SHARED_DATA@0x0 0x2000
|
||||
VBLOCK_DEV@0x2000 0x2000
|
||||
}
|
||||
RW_VPD@0x1f8000 0x2000
|
||||
RW_UNUSED@0x1fa000 0x6000
|
||||
RW_LEGACY(CBFS)@0x200000 0x200000
|
||||
WP_RO@0x400000 0x200000 {
|
||||
RO_VPD@0x0 0x4000
|
||||
RO_UNUSED@0x4000 0xc000
|
||||
RO_SECTION@0x10000 0x1f0000 {
|
||||
FMAP@0x0 0x800
|
||||
RO_FRID@0x800 0x40
|
||||
RO_FRID_PAD@0x840 0x7c0
|
||||
GBB@0x1000 0xef000
|
||||
COREBOOT(CBFS)@0xf0000 0x100000
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,132 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007-2008 coresystems GmbH
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
entries
|
||||
|
||||
#start-bit length config config-ID name
|
||||
#0 8 r 0 seconds
|
||||
#8 8 r 0 alarm_seconds
|
||||
#16 8 r 0 minutes
|
||||
#24 8 r 0 alarm_minutes
|
||||
#32 8 r 0 hours
|
||||
#40 8 r 0 alarm_hours
|
||||
#48 8 r 0 day_of_week
|
||||
#56 8 r 0 day_of_month
|
||||
#64 8 r 0 month
|
||||
#72 8 r 0 year
|
||||
# -----------------------------------------------------------------
|
||||
# Status Register A
|
||||
#80 4 r 0 rate_select
|
||||
#84 3 r 0 REF_Clock
|
||||
#87 1 r 0 UIP
|
||||
# -----------------------------------------------------------------
|
||||
# Status Register B
|
||||
#88 1 r 0 auto_switch_DST
|
||||
#89 1 r 0 24_hour_mode
|
||||
#90 1 r 0 binary_values_enable
|
||||
#91 1 r 0 square-wave_out_enable
|
||||
#92 1 r 0 update_finished_enable
|
||||
#93 1 r 0 alarm_interrupt_enable
|
||||
#94 1 r 0 periodic_interrupt_enable
|
||||
#95 1 r 0 disable_clock_updates
|
||||
# -----------------------------------------------------------------
|
||||
# Status Register C
|
||||
#96 4 r 0 status_c_rsvd
|
||||
#100 1 r 0 uf_flag
|
||||
#101 1 r 0 af_flag
|
||||
#102 1 r 0 pf_flag
|
||||
#103 1 r 0 irqf_flag
|
||||
# -----------------------------------------------------------------
|
||||
# Status Register D
|
||||
#104 7 r 0 status_d_rsvd
|
||||
#111 1 r 0 valid_cmos_ram
|
||||
# -----------------------------------------------------------------
|
||||
# Diagnostic Status Register
|
||||
#112 8 r 0 diag_rsvd1
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
0 120 r 0 reserved_memory
|
||||
#120 264 r 0 unused
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||
384 1 e 4 boot_option
|
||||
388 4 h 0 reboot_counter
|
||||
#390 2 r 0 unused?
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
# coreboot config options: console
|
||||
392 3 e 5 baud_rate
|
||||
395 4 e 6 debug_level
|
||||
#399 1 r 0 unused
|
||||
|
||||
# coreboot config options: cpu
|
||||
400 1 e 2 hyper_threading
|
||||
#401 7 r 0 unused
|
||||
|
||||
# coreboot config options: southbridge
|
||||
408 1 e 1 nmi
|
||||
409 2 e 7 power_on_after_fail
|
||||
#411 5 r 0 unused
|
||||
|
||||
# coreboot config options: bootloader
|
||||
#Used by ChromeOS:
|
||||
416 128 r 0 vbnv
|
||||
#544 440 r 0 unused
|
||||
|
||||
# SandyBridge MRC Scrambler Seed values
|
||||
896 32 r 0 mrc_scrambler_seed
|
||||
928 32 r 0 mrc_scrambler_seed_s3
|
||||
|
||||
# coreboot config options: check sums
|
||||
984 16 h 0 check_sum
|
||||
#1000 24 r 0 amd_reserved
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
5 0 115200
|
||||
5 1 57600
|
||||
5 2 38400
|
||||
5 3 19200
|
||||
5 4 9600
|
||||
5 5 4800
|
||||
5 6 2400
|
||||
5 7 1200
|
||||
6 1 Emergency
|
||||
6 2 Alert
|
||||
6 3 Critical
|
||||
6 4 Error
|
||||
6 5 Warning
|
||||
6 6 Notice
|
||||
6 7 Info
|
||||
6 8 Debug
|
||||
6 9 Spew
|
||||
7 0 Disable
|
||||
7 1 Enable
|
||||
7 2 Keep
|
||||
# -----------------------------------------------------------------
|
||||
checksums
|
||||
|
||||
checksum 392 415 984
|
||||
|
|
@ -1,119 +0,0 @@
|
|||
chip soc/intel/broadwell
|
||||
|
||||
# Disable eDP Hotplug
|
||||
register "gpu_dp_d_hotplug" = "0x00"
|
||||
|
||||
# Enable DisplayPort C Hotplug with 6ms pulse
|
||||
register "gpu_dp_c_hotplug" = "0x06"
|
||||
|
||||
# Enable HDMI Hotplug with 6ms pulse
|
||||
register "gpu_dp_b_hotplug" = "0x06"
|
||||
|
||||
register "pirqa_routing" = "0x8b"
|
||||
register "pirqb_routing" = "0x8a"
|
||||
register "pirqc_routing" = "0x8b"
|
||||
register "pirqd_routing" = "0x8b"
|
||||
register "pirqe_routing" = "0x80"
|
||||
register "pirqf_routing" = "0x80"
|
||||
register "pirqg_routing" = "0x80"
|
||||
register "pirqh_routing" = "0x80"
|
||||
|
||||
# SuperIO range is 0x700-0x73f
|
||||
register "gen2_dec" = "0x003c0701"
|
||||
|
||||
register "alt_gp_smi_en" = "0x0000"
|
||||
register "gpe0_en_1" = "0x00000000"
|
||||
register "gpe0_en_2" = "0x00000000"
|
||||
register "gpe0_en_3" = "0x00000000"
|
||||
register "gpe0_en_4" = "0x00000000"
|
||||
|
||||
register "sata_port_map" = "0x1"
|
||||
register "sata_devslp_disable" = "0x1"
|
||||
|
||||
register "sio_acpi_mode" = "0"
|
||||
register "sio_i2c0_voltage" = "0" # 3.3V
|
||||
register "sio_i2c1_voltage" = "0" # 3.3V
|
||||
|
||||
# Force enable ASPM for PCIe Port 4
|
||||
register "pcie_port_force_aspm" = "0x10"
|
||||
|
||||
# Enable port coalescing
|
||||
register "pcie_port_coalesce" = "1"
|
||||
|
||||
# Disable PCIe CLKOUT 1,5 and CLKOUT_XDP
|
||||
register "icc_clock_disable" = "0x01220000"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # host bridge
|
||||
device pci 02.0 on end # vga controller
|
||||
device pci 03.0 on end # mini-hd audio
|
||||
device pci 13.0 off end # Smart Sound Audio DSP
|
||||
device pci 14.0 on end # USB3 XHCI
|
||||
device pci 15.0 off end # Serial I/O DMA
|
||||
device pci 15.1 off end # I2C0
|
||||
device pci 15.2 off end # I2C1
|
||||
device pci 15.3 off end # GSPI0
|
||||
device pci 15.4 off end # GSPI1
|
||||
device pci 15.5 off end # UART0
|
||||
device pci 15.6 off end # UART1
|
||||
device pci 16.0 on end # Management Engine Interface 1
|
||||
device pci 16.1 off end # Management Engine Interface 2
|
||||
device pci 16.2 off end # Management Engine IDE-R
|
||||
device pci 16.3 off end # Management Engine KT
|
||||
device pci 17.0 off end # SDIO
|
||||
device pci 19.0 off end # GbE
|
||||
device pci 1b.0 on end # High Definition Audio
|
||||
device pci 1c.0 off end # PCIe Port #1
|
||||
device pci 1c.1 off end # PCIe Port #2
|
||||
device pci 1c.2 on end # PCIe Port #3
|
||||
device pci 1c.3 on end # PCIe Port #4
|
||||
device pci 1c.4 on end # PCIe Port #5
|
||||
device pci 1c.5 off end # PCIe Port #6
|
||||
device pci 1d.0 on end # USB2 EHCI
|
||||
device pci 1e.0 off end # PCI bridge
|
||||
device pci 1f.0 on
|
||||
chip superio/ite/it8772f
|
||||
# Skip keyboard init
|
||||
register "skip_keyboard" = "1"
|
||||
# Enable PECI on TMPIN3
|
||||
register "peci_tmpin" = "3"
|
||||
# Enable FAN2
|
||||
register "fan2_enable" = "1"
|
||||
|
||||
device pnp 2e.0 off end # FDC
|
||||
device pnp 2e.1 on # Serial Port 1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.4 on # Environment Controller
|
||||
io 0x60 = 0x700
|
||||
io 0x62 = 0x710
|
||||
irq 0x70 = 0x09
|
||||
irq 0xf2 = 0x20
|
||||
irq 0xf4 = 0x0
|
||||
irq 0xfa = 0x12
|
||||
end
|
||||
device pnp 2e.7 on # GPIO
|
||||
io 0x60 = 0x720
|
||||
io 0x62 = 0x730
|
||||
end
|
||||
device pnp 2e.5 off
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
end # Keyboard
|
||||
device pnp 2e.6 off
|
||||
irq 0x70 = 12
|
||||
end # Mouse
|
||||
device pnp 2e.a off end # IR
|
||||
end
|
||||
end # LPC bridge
|
||||
device pci 1f.2 on end # SATA Controller
|
||||
device pci 1f.3 on end # SMBus
|
||||
device pci 1f.6 on end # Thermal
|
||||
end
|
||||
end
|
||||
|
|
@ -1,56 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
DefinitionBlock(
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
0x02, // DSDT revision: ACPI v2.0
|
||||
"COREv4", // OEM id
|
||||
"COREBOOT", // OEM table id
|
||||
0x20110725 // OEM revision
|
||||
)
|
||||
{
|
||||
// Some generic macros
|
||||
#include "acpi/platform.asl"
|
||||
|
||||
// global NVS and variables
|
||||
#include <soc/intel/broadwell/acpi/globalnvs.asl>
|
||||
|
||||
// General Purpose Events
|
||||
//#include "acpi/gpe.asl"
|
||||
|
||||
// CPU
|
||||
#include <soc/intel/broadwell/acpi/cpu.asl>
|
||||
|
||||
Scope (\_SB) {
|
||||
Device (PCI0)
|
||||
{
|
||||
#include <soc/intel/broadwell/acpi/systemagent.asl>
|
||||
#include <soc/intel/broadwell/acpi/pch.asl>
|
||||
}
|
||||
}
|
||||
|
||||
// Thermal handler
|
||||
#include "acpi/thermal.asl"
|
||||
|
||||
// Chrome OS specific
|
||||
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
|
||||
|
||||
// Chipset specific sleep states
|
||||
#include <soc/intel/broadwell/acpi/sleepstates.asl>
|
||||
|
||||
// Mainboard specific
|
||||
#include "acpi/mainboard.asl"
|
||||
}
|
||||
|
|
@ -1,154 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include <device/pci.h>
|
||||
#include <soc/acpi.h>
|
||||
#include <cpu/x86/smm.h>
|
||||
#include <soc/pch.h>
|
||||
#include <soc/iomap.h>
|
||||
|
||||
void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
|
||||
{
|
||||
acpi_header_t *header = &(fadt->header);
|
||||
u16 pmbase = ACPI_BASE_ADDRESS;
|
||||
|
||||
memset((void *) fadt, 0, sizeof(acpi_fadt_t));
|
||||
memcpy(header->signature, "FACP", 4);
|
||||
header->length = sizeof(acpi_fadt_t);
|
||||
header->revision = 5;
|
||||
memcpy(header->oem_id, OEM_ID, 6);
|
||||
memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
|
||||
memcpy(header->asl_compiler_id, ASLC, 4);
|
||||
header->asl_compiler_revision = 1;
|
||||
|
||||
fadt->firmware_ctrl = (unsigned long) facs;
|
||||
fadt->dsdt = (unsigned long) dsdt;
|
||||
fadt->model = 1;
|
||||
fadt->preferred_pm_profile = PM_MOBILE;
|
||||
|
||||
fadt->sci_int = 0x9;
|
||||
fadt->smi_cmd = APM_CNT;
|
||||
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
|
||||
fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
|
||||
fadt->s4bios_req = 0x0;
|
||||
fadt->pstate_cnt = 0;
|
||||
|
||||
fadt->pm1a_evt_blk = pmbase;
|
||||
fadt->pm1b_evt_blk = 0x0;
|
||||
fadt->pm1a_cnt_blk = pmbase + 0x4;
|
||||
fadt->pm1b_cnt_blk = 0x0;
|
||||
fadt->pm2_cnt_blk = pmbase + 0x50;
|
||||
fadt->pm_tmr_blk = pmbase + 0x8;
|
||||
fadt->gpe0_blk = pmbase + 0x80;
|
||||
fadt->gpe1_blk = 0;
|
||||
|
||||
fadt->pm1_evt_len = 4;
|
||||
fadt->pm1_cnt_len = 2;
|
||||
fadt->pm2_cnt_len = 1;
|
||||
fadt->pm_tmr_len = 4;
|
||||
fadt->gpe0_blk_len = 32;
|
||||
fadt->gpe1_blk_len = 0;
|
||||
fadt->gpe1_base = 0;
|
||||
fadt->cst_cnt = 0;
|
||||
fadt->p_lvl2_lat = 1;
|
||||
fadt->p_lvl3_lat = 87;
|
||||
fadt->flush_size = 1024;
|
||||
fadt->flush_stride = 16;
|
||||
fadt->duty_offset = 1;
|
||||
fadt->duty_width = 0;
|
||||
fadt->day_alrm = 0xd;
|
||||
fadt->mon_alrm = 0x00;
|
||||
fadt->century = 0x00;
|
||||
fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
|
||||
|
||||
fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
|
||||
ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
|
||||
ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |
|
||||
ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
|
||||
|
||||
fadt->reset_reg.space_id = 1;
|
||||
fadt->reset_reg.bit_width = 8;
|
||||
fadt->reset_reg.bit_offset = 0;
|
||||
fadt->reset_reg.resv = 0;
|
||||
fadt->reset_reg.addrl = 0xcf9;
|
||||
fadt->reset_reg.addrh = 0;
|
||||
|
||||
fadt->reset_value = 6;
|
||||
fadt->x_firmware_ctl_l = (unsigned long)facs;
|
||||
fadt->x_firmware_ctl_h = 0;
|
||||
fadt->x_dsdt_l = (unsigned long)dsdt;
|
||||
fadt->x_dsdt_h = 0;
|
||||
|
||||
fadt->x_pm1a_evt_blk.space_id = 1;
|
||||
fadt->x_pm1a_evt_blk.bit_width = 32;
|
||||
fadt->x_pm1a_evt_blk.bit_offset = 0;
|
||||
fadt->x_pm1a_evt_blk.resv = 0;
|
||||
fadt->x_pm1a_evt_blk.addrl = pmbase;
|
||||
fadt->x_pm1a_evt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1b_evt_blk.space_id = 1;
|
||||
fadt->x_pm1b_evt_blk.bit_width = 0;
|
||||
fadt->x_pm1b_evt_blk.bit_offset = 0;
|
||||
fadt->x_pm1b_evt_blk.resv = 0;
|
||||
fadt->x_pm1b_evt_blk.addrl = 0x0;
|
||||
fadt->x_pm1b_evt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1a_cnt_blk.space_id = 1;
|
||||
fadt->x_pm1a_cnt_blk.bit_width = 16;
|
||||
fadt->x_pm1a_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm1a_cnt_blk.resv = 0;
|
||||
fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
|
||||
fadt->x_pm1a_cnt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1b_cnt_blk.space_id = 1;
|
||||
fadt->x_pm1b_cnt_blk.bit_width = 0;
|
||||
fadt->x_pm1b_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm1b_cnt_blk.resv = 0;
|
||||
fadt->x_pm1b_cnt_blk.addrl = 0x0;
|
||||
fadt->x_pm1b_cnt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm2_cnt_blk.space_id = 1;
|
||||
fadt->x_pm2_cnt_blk.bit_width = 8;
|
||||
fadt->x_pm2_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm2_cnt_blk.resv = 0;
|
||||
fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
|
||||
fadt->x_pm2_cnt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm_tmr_blk.space_id = 1;
|
||||
fadt->x_pm_tmr_blk.bit_width = 32;
|
||||
fadt->x_pm_tmr_blk.bit_offset = 0;
|
||||
fadt->x_pm_tmr_blk.resv = 0;
|
||||
fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
|
||||
fadt->x_pm_tmr_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_gpe0_blk.space_id = 0;
|
||||
fadt->x_gpe0_blk.bit_width = 0;
|
||||
fadt->x_gpe0_blk.bit_offset = 0;
|
||||
fadt->x_gpe0_blk.resv = 0;
|
||||
fadt->x_gpe0_blk.addrl = 0;
|
||||
fadt->x_gpe0_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_gpe1_blk.space_id = 1;
|
||||
fadt->x_gpe1_blk.bit_width = 0;
|
||||
fadt->x_gpe1_blk.bit_offset = 0;
|
||||
fadt->x_gpe1_blk.resv = 0;
|
||||
fadt->x_gpe1_blk.addrl = 0x0;
|
||||
fadt->x_gpe1_blk.addrh = 0x0;
|
||||
|
||||
header->checksum =
|
||||
acpi_checksum((void *) fadt, header->length);
|
||||
}
|
||||
|
|
@ -1,109 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2013 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* coreboot specific header */
|
||||
0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283
|
||||
0x10ec0283, // Subsystem ID
|
||||
0x0000000c, // Number of jacks (NID entries)
|
||||
|
||||
/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10ec0283 */
|
||||
0x00172083,
|
||||
0x00172102,
|
||||
0x001722ec,
|
||||
0x00172310,
|
||||
|
||||
/* Pin Widget Verb Table */
|
||||
|
||||
/* Pin Complex (NID 0x12) DMIC */
|
||||
0x01271cf0,
|
||||
0x01271d11,
|
||||
0x01271e11,
|
||||
0x01271f41,
|
||||
|
||||
/* Pin Complex (NID 0x14) SPKR-OUT PORTD */
|
||||
0x01471cf0,
|
||||
0x01471d11,
|
||||
0x01471e11,
|
||||
0x01471f40,
|
||||
|
||||
/* Pin Complex (NID 0x17) */
|
||||
0x01771cf0,
|
||||
0x01771d11,
|
||||
0x01771e11,
|
||||
0x01771f41,
|
||||
|
||||
/* Pin Complex (NID 0x18) MIC1 PORTB */
|
||||
0x01971c11, // group 1, cap 1
|
||||
0x01971d10, // black, jack detect
|
||||
0x01971ea7, // mic in, analog
|
||||
0x01971f03, // connector, left panel
|
||||
|
||||
/* Pin Complex (NID 0x19) MIC2 PORTF */
|
||||
0x01871cf0,
|
||||
0x01871d11,
|
||||
0x01871e11,
|
||||
0x01871f41,
|
||||
|
||||
/* Pin Complex (NID 0x1A) LINE1 PORTC */
|
||||
0x01a71cf0,
|
||||
0x01a71d11,
|
||||
0x01a71e11,
|
||||
0x01a71f41,
|
||||
|
||||
/* Pin Complex (NID 0x1B) LINE2 PORTE */
|
||||
0x01a71cf0,
|
||||
0x01a71d11,
|
||||
0x01a71e11,
|
||||
0x01a71f41,
|
||||
|
||||
/* Pin Complex (NID 0x1d) PCBeep */
|
||||
0x01d71c2d, // eapd low on ex-amp, laptop, custom enable
|
||||
0x01d71d81, // mute spkr on hpout
|
||||
0x01d71e15, // pcbeep en able, checksum
|
||||
0x01d71f40, // no physical, internal
|
||||
|
||||
/* Pin Complex (NID 0x1E) SPDIF-OUT */
|
||||
0x01e71cf0,
|
||||
0x01e71d11,
|
||||
0x01e71e11,
|
||||
0x01e71f41,
|
||||
|
||||
/* Pin Complex (NID 0x21) HPOUT PORT-I */
|
||||
0x02171c1f, // group1,
|
||||
0x02171d10, // black, jack detect
|
||||
0x02171e21, // HPOut, 1/8 stereo
|
||||
0x02171f03, // connector, left panel
|
||||
|
||||
/* Undocumented settings from Realtek (needed for beep_gen) */
|
||||
/* Widget node 0x20 */
|
||||
0x02050010,
|
||||
0x02040c20,
|
||||
0x0205001b,
|
||||
0x0204081b,
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {
|
||||
0x00170500, /* power up everything (codec, dac, adc, mixers) */
|
||||
0x01470740, /* enable speaker out */
|
||||
0x01470c02, /* set speaker EAPD pin */
|
||||
0x0143b01f, /* unmute speaker */
|
||||
0x00c37100, /* unmute mixer nid 0xc input 1 */
|
||||
0x00b37410, /* unmute mixer nid 0xb beep input and set volume */
|
||||
};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
|
@ -1,192 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <cbfs.h>
|
||||
#include <string.h>
|
||||
#include <types.h>
|
||||
#include <arch/io.h>
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <fmap.h>
|
||||
#include <southbridge/intel/bd82x6x/pch.h>
|
||||
#include "onboard.h"
|
||||
|
||||
static unsigned int search(char *p, u8 *a, unsigned int lengthp,
|
||||
unsigned int lengtha)
|
||||
{
|
||||
int i, j;
|
||||
|
||||
/* Searching */
|
||||
for (j = 0; j <= lengtha - lengthp; j++) {
|
||||
for (i = 0; i < lengthp && p[i] == a[i + j]; i++)
|
||||
;
|
||||
if (i >= lengthp)
|
||||
return j;
|
||||
}
|
||||
return lengtha;
|
||||
}
|
||||
|
||||
static unsigned char get_hex_digit(u8 *offset)
|
||||
{
|
||||
unsigned char retval = 0;
|
||||
|
||||
retval = *offset - '0';
|
||||
if (retval > 0x09) {
|
||||
retval = *offset - 'A' + 0x0A;
|
||||
if (retval > 0x0F)
|
||||
retval = *offset - 'a' + 0x0a;
|
||||
}
|
||||
if (retval > 0x0F) {
|
||||
printk(BIOS_DEBUG, "Error: Invalid Hex digit found: %c - 0x%02x\n",
|
||||
*offset, *offset);
|
||||
retval = 0;
|
||||
}
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
static int get_mac_address(u32 *high_dword, u32 *low_dword,
|
||||
u8 *search_address, u32 search_length)
|
||||
{
|
||||
char key[] = "ethernet_mac";
|
||||
unsigned int offset;
|
||||
int i;
|
||||
|
||||
offset = search(key, search_address, sizeof(key) - 1, search_length);
|
||||
if (offset == search_length) {
|
||||
printk(BIOS_DEBUG,
|
||||
"Error: Could not locate '%s' in VPD\n", key);
|
||||
return 0;
|
||||
}
|
||||
printk(BIOS_DEBUG, "Located '%s' in VPD\n", key);
|
||||
|
||||
offset += sizeof(key); /* move to next character */
|
||||
*high_dword = 0;
|
||||
|
||||
/* Fetch the MAC address and put the octets in the correct order to
|
||||
* be programmed.
|
||||
*
|
||||
* From RTL8105E_Series_EEPROM-Less_App_Note_1.1
|
||||
* If the MAC address is 001122334455h:
|
||||
* Write 33221100h to I/O register offset 0x00 via double word access
|
||||
* Write 00005544h to I/O register offset 0x04 via double word access
|
||||
*/
|
||||
|
||||
for (i = 0; i < 4; i++) {
|
||||
*high_dword |= (get_hex_digit(search_address + offset)
|
||||
<< (4 + (i * 8)));
|
||||
*high_dword |= (get_hex_digit(search_address + offset + 1)
|
||||
<< (i * 8));
|
||||
offset += 3;
|
||||
}
|
||||
|
||||
*low_dword = 0;
|
||||
for (i = 0; i < 2; i++) {
|
||||
*low_dword |= (get_hex_digit(search_address + offset)
|
||||
<< (4 + (i * 8)));
|
||||
*low_dword |= (get_hex_digit(search_address + offset + 1)
|
||||
<< (i * 8));
|
||||
offset += 3;
|
||||
}
|
||||
|
||||
return *high_dword | *low_dword;
|
||||
}
|
||||
|
||||
static void program_mac_address(u16 io_base)
|
||||
{
|
||||
void *search_address = NULL;
|
||||
size_t search_length = -1;
|
||||
|
||||
/* Default MAC Address of A0:00:BA:D0:0B:AD */
|
||||
u32 high_dword = 0xD0BA00A0; /* high dword of mac address */
|
||||
u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */
|
||||
|
||||
if (IS_ENABLED(CONFIG_CHROMEOS)) {
|
||||
struct region_device rdev;
|
||||
|
||||
if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) {
|
||||
search_address = rdev_mmap_full(&rdev);
|
||||
|
||||
if (search_address != NULL)
|
||||
search_length = region_device_sz(&rdev);
|
||||
}
|
||||
} else {
|
||||
search_address = cbfs_boot_map_with_leak("vpd.bin",
|
||||
CBFS_TYPE_RAW,
|
||||
&search_length);
|
||||
}
|
||||
|
||||
if (search_address == NULL)
|
||||
printk(BIOS_ERR, "LAN: VPD not found.\n");
|
||||
else
|
||||
get_mac_address(&high_dword, &low_dword, search_address,
|
||||
search_length);
|
||||
|
||||
if (io_base) {
|
||||
printk(BIOS_DEBUG, "Realtek NIC io_base = 0x%04x\n", io_base);
|
||||
printk(BIOS_DEBUG, "Programming MAC Address\n");
|
||||
|
||||
/* Disable register protection */
|
||||
outb(0xc0, io_base + 0x50);
|
||||
outl(high_dword, io_base);
|
||||
outl(low_dword, io_base + 0x04);
|
||||
outb(0x60, io_base + 54);
|
||||
/* Enable register protection again */
|
||||
outb(0x00, io_base + 0x50);
|
||||
}
|
||||
}
|
||||
|
||||
void lan_init(void)
|
||||
{
|
||||
u16 io_base = 0;
|
||||
struct device *ethernet_dev = NULL;
|
||||
|
||||
/* Get NIC's IO base address */
|
||||
ethernet_dev = dev_find_device(GUADO_NIC_VENDOR_ID,
|
||||
GUADO_NIC_DEVICE_ID, 0);
|
||||
if (ethernet_dev != NULL) {
|
||||
io_base = pci_read_config16(ethernet_dev, 0x10) & 0xfffe;
|
||||
|
||||
/*
|
||||
* Battery life time - LAN PCIe should enter ASPM L1 to save
|
||||
* power when LAN connection is idle.
|
||||
* enable CLKREQ: LAN pci config space 0x81h=01
|
||||
*/
|
||||
pci_write_config8(ethernet_dev, 0x81, 0x01);
|
||||
}
|
||||
|
||||
if (io_base) {
|
||||
/* Program MAC address based on VPD data */
|
||||
program_mac_address(io_base);
|
||||
|
||||
/*
|
||||
* Program NIC LEDS
|
||||
*
|
||||
* RTL8105E Series EEPROM-Less Application Note,
|
||||
* Section 5.6 LED Mode Configuration
|
||||
*
|
||||
* Step1: Write C0h to I/O register 0x50 via byte access to
|
||||
* disable 'register protection'
|
||||
* Step2: Write xx001111b to I/O register 0x52 via byte access
|
||||
* (bit7 is LEDS1 and bit6 is LEDS0)
|
||||
* Step3: Write 0x00 to I/O register 0x50 via byte access to
|
||||
* enable 'register protection'
|
||||
*/
|
||||
outb(0xc0, io_base + 0x50); /* Disable protection */
|
||||
outb((GUADO_NIC_LED_MODE << 6) | 0x0f, io_base + 0x52);
|
||||
outb(0x00, io_base + 0x50); /* Enable register protection */
|
||||
}
|
||||
}
|
||||
|
|
@ -1,44 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/io.h>
|
||||
#include <vendorcode/google/chromeos/chromeos.h>
|
||||
#include "onboard.h"
|
||||
|
||||
void mainboard_suspend_resume(void)
|
||||
{
|
||||
/* Call SMM finalize() handlers before resume */
|
||||
outb(0xcb, 0xb2);
|
||||
}
|
||||
|
||||
static void mainboard_init(device_t dev)
|
||||
{
|
||||
lan_init();
|
||||
}
|
||||
|
||||
// mainboard_enable is executed as first thing after
|
||||
// enumerate_buses().
|
||||
|
||||
static void mainboard_enable(device_t dev)
|
||||
{
|
||||
dev->ops->init = mainboard_init;
|
||||
dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
|
|
@ -1,42 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef ONBOARD_H
|
||||
#define ONBOARD_H
|
||||
|
||||
#ifndef __ACPI__
|
||||
void lan_init(void);
|
||||
#endif
|
||||
|
||||
/* defines for programming the MAC address */
|
||||
#define GUADO_NIC_VENDOR_ID 0x10EC
|
||||
#define GUADO_NIC_DEVICE_ID 0x8168
|
||||
|
||||
/* 0x00: White LINK LED and Amber ACTIVE LED */
|
||||
#define GUADO_NIC_LED_MODE 0x00
|
||||
|
||||
/* NIC wake is GPIO 8 */
|
||||
#define GUADO_NIC_WAKE_GPIO 8
|
||||
|
||||
/* WLAN wake is GPIO 10 */
|
||||
#define GUADO_WLAN_WAKE_GPIO 10
|
||||
|
||||
/* IT8772F defs */
|
||||
#define IT8772F_BASE 0x2e
|
||||
#define IT8772F_SERIAL_DEV PNP_DEV(IT8772F_BASE, IT8772F_SP1)
|
||||
#define IT8772F_GPIO_DEV PNP_DEV(IT8772F_BASE, IT8772F_GPIO)
|
||||
#define IT8772F_DUMMY_DEV PNP_DEV(IT8772F_BASE, 0)
|
||||
|
||||
#endif
|
||||
|
|
@ -1,64 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2010 coresystems GmbH
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <cbfs.h>
|
||||
#include <console/console.h>
|
||||
#include <string.h>
|
||||
#include <ec/google/chromeec/ec.h>
|
||||
#include <soc/gpio.h>
|
||||
#include <soc/pei_data.h>
|
||||
#include <soc/pei_wrapper.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <mainboard/google/guado/spd/spd.h>
|
||||
#include <superio/ite/common/ite.h>
|
||||
#include <superio/ite/it8772f/it8772f.h>
|
||||
#include "gpio.h"
|
||||
#include "onboard.h"
|
||||
|
||||
|
||||
void mainboard_romstage_entry(struct romstage_params *rp)
|
||||
{
|
||||
struct pei_data pei_data;
|
||||
|
||||
post_code(0x32);
|
||||
|
||||
/* Initialize GPIOs */
|
||||
init_gpios(mainboard_gpio_config);
|
||||
|
||||
/* Fill out PEI DATA */
|
||||
memset(&pei_data, 0, sizeof(pei_data));
|
||||
mainboard_fill_pei_data(&pei_data);
|
||||
mainboard_fill_spd_data(&pei_data);
|
||||
rp->pei_data = &pei_data;
|
||||
|
||||
/* Call into the real romstage main with this board's attributes. */
|
||||
romstage_common(rp);
|
||||
}
|
||||
|
||||
void mainboard_pre_console_init(void)
|
||||
{
|
||||
/* Early SuperIO setup */
|
||||
ite_kill_watchdog(IT8772F_GPIO_DEV);
|
||||
it8772f_ac_resume_southbridge(IT8772F_DUMMY_DEV);
|
||||
ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
|
||||
/* Turn On GPIO10.LED */
|
||||
it8772f_gpio_led(IT8772F_GPIO_DEV, 1 /* set */, 0x01 /* select */,
|
||||
0x00 /* polarity: non-inverting */, 0x00 /* 0=pulldown */,
|
||||
0x01 /* output */, 0x01 /* 1=Simple IO function */,
|
||||
SIO_GPIO_BLINK_GPIO10, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ);
|
||||
|
||||
}
|
||||
|
|
@ -1,90 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008-2009 coresystems GmbH
|
||||
* Copyright 2014 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/io.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/x86/smm.h>
|
||||
#include <soc/pm.h>
|
||||
#include <soc/smm.h>
|
||||
#include <elog.h>
|
||||
#include <ec/google/chromeec/ec.h>
|
||||
#include <soc/gpio.h>
|
||||
#include <soc/iomap.h>
|
||||
#include <soc/nvs.h>
|
||||
#include <soc/pm.h>
|
||||
#include <soc/smm.h>
|
||||
#include <superio/ite/it8772f/it8772f.h>
|
||||
#include "onboard.h"
|
||||
|
||||
|
||||
int mainboard_io_trap_handler(int smif)
|
||||
{
|
||||
switch (smif) {
|
||||
case 0x99:
|
||||
printk(BIOS_DEBUG, "Sample\n");
|
||||
smm_get_gnvs()->smif = 0;
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* On success, the IO Trap Handler returns 0
|
||||
* On failure, the IO Trap Handler returns a value != 0
|
||||
*
|
||||
* For now, we force the return value to 0 and log all traps to
|
||||
* see what's going on.
|
||||
*/
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* gpi_sts is GPIO 47:32 */
|
||||
void mainboard_smi_gpi(u32 gpi_sts)
|
||||
{
|
||||
}
|
||||
|
||||
void mainboard_smi_sleep(u8 slp_typ)
|
||||
{
|
||||
/* Disable USB charging if required */
|
||||
switch (slp_typ) {
|
||||
case ACPI_S3:
|
||||
it8772f_gpio_led(IT8772F_GPIO_DEV, 1 /* set */, 0x01 /* select */,
|
||||
0x01 /* polarity */, 0x01 /* 1=pullup */,
|
||||
0x01 /* output */, 0x00, /* 0=Alternate function */
|
||||
SIO_GPIO_BLINK_GPIO10, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ);
|
||||
break;
|
||||
case ACPI_S5:
|
||||
it8772f_gpio_led(IT8772F_GPIO_DEV, 1 /* set */, 0x01 /* select */,
|
||||
0x00 /* polarity: non-inverting */, 0x00 /* 0=pulldown */,
|
||||
0x01 /* output */, 0x01 /* 1=Simple IO function */,
|
||||
SIO_GPIO_BLINK_GPIO10, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
int mainboard_smi_apmc(u8 apmc)
|
||||
{
|
||||
switch (apmc) {
|
||||
case APM_CNT_ACPI_ENABLE:
|
||||
break;
|
||||
case APM_CNT_ACPI_DISABLE:
|
||||
break;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1,16 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2014 Google Inc.
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
|
||||
romstage-y += spd.c
|
||||
|
|
@ -1,31 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <soc/pei_data.h>
|
||||
#include <mainboard/google/guado/spd/spd.h>
|
||||
|
||||
/* Copy SPD data for on-board memory */
|
||||
void mainboard_fill_spd_data(struct pei_data *pei_data)
|
||||
{
|
||||
pei_data->spd_addresses[0] = 0xa0;
|
||||
pei_data->spd_addresses[1] = 0x00;
|
||||
pei_data->spd_addresses[2] = 0xa4;
|
||||
pei_data->spd_addresses[3] = 0x00;
|
||||
pei_data->dimm_channel0_disabled = 2;
|
||||
pei_data->dimm_channel1_disabled = 2;
|
||||
// Enable 2x refresh mode
|
||||
pei_data->ddr_refresh_2x = 1;
|
||||
pei_data->dq_pins_interleaved = 1;
|
||||
}
|
||||
|
|
@ -1,22 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef MAINBOARD_SPD_H
|
||||
#define MAINBOARD_SPD_H
|
||||
|
||||
struct pei_data;
|
||||
void mainboard_fill_spd_data(struct pei_data *pei_data);
|
||||
|
||||
#endif
|
||||
|
|
@ -1,7 +1,5 @@
|
|||
if BOARD_GOOGLE_JECHT
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
def_bool y
|
||||
config BOARD_GOOGLE_BASEBOARD_JECHT
|
||||
def_bool n
|
||||
select SOC_INTEL_BROADWELL
|
||||
select BOARD_ROMSIZE_KB_8192
|
||||
select SUPERIO_ITE_IT8772F
|
||||
|
|
@ -11,7 +9,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
|
|||
select HAVE_SMI_HANDLER
|
||||
select MAINBOARD_HAS_CHROMEOS
|
||||
select MAINBOARD_HAS_LPC_TPM
|
||||
select INTEL_INT15
|
||||
|
||||
if BOARD_GOOGLE_BASEBOARD_JECHT
|
||||
|
||||
config CHROMEOS
|
||||
select CHROMEOS_RAMOOPS_DYNAMIC
|
||||
|
|
@ -23,9 +22,28 @@ config MAINBOARD_DIR
|
|||
string
|
||||
default google/jecht
|
||||
|
||||
|
||||
config VARIANT_DIR
|
||||
string
|
||||
default "guado" if BOARD_GOOGLE_GUADO
|
||||
default "jecht" if BOARD_GOOGLE_JECHT
|
||||
default "rikku" if BOARD_GOOGLE_RIKKU
|
||||
default "tidus" if BOARD_GOOGLE_TIDUS
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "Jecht"
|
||||
default "Guado" if BOARD_GOOGLE_GUADO
|
||||
default "Jecht" if BOARD_GOOGLE_JECHT
|
||||
default "Rikku" if BOARD_GOOGLE_RIKKU
|
||||
default "Tidus" if BOARD_GOOGLE_TIDUS
|
||||
|
||||
config GBB_HWID
|
||||
string
|
||||
depends on CHROMEOS
|
||||
default "GUADO TEST A-A 7416" if BOARD_GOOGLE_GUADO
|
||||
default "JECHT TEST A-A 8958" if BOARD_GOOGLE_JECHT
|
||||
default "RIKKU TEST A-A 0702" if BOARD_GOOGLE_RIKKU
|
||||
default "TIDUS TEST A-A 0595" if BOARD_GOOGLE_TIDUS
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
|
|
@ -33,7 +51,7 @@ config MAX_CPUS
|
|||
|
||||
config VGA_BIOS_FILE
|
||||
string
|
||||
default "pci8086,0166.rom"
|
||||
default "pci8086,0406.rom"
|
||||
|
||||
config HAVE_IFD_BIN
|
||||
bool
|
||||
|
|
@ -43,8 +61,4 @@ config HAVE_ME_BIN
|
|||
bool
|
||||
default n
|
||||
|
||||
config GBB_HWID
|
||||
string
|
||||
depends on CHROMEOS
|
||||
default "JECHT TEST A-A 8958"
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -1,2 +1,15 @@
|
|||
config BOARD_GOOGLE_GUADO
|
||||
bool "Guado"
|
||||
select BOARD_GOOGLE_BASEBOARD_JECHT
|
||||
|
||||
config BOARD_GOOGLE_JECHT
|
||||
bool "Jecht"
|
||||
select BOARD_GOOGLE_BASEBOARD_JECHT
|
||||
|
||||
config BOARD_GOOGLE_RIKKU
|
||||
bool "Rikku"
|
||||
select BOARD_GOOGLE_BASEBOARD_JECHT
|
||||
|
||||
config BOARD_GOOGLE_TIDUS
|
||||
bool "Tidus"
|
||||
select BOARD_GOOGLE_BASEBOARD_JECHT
|
||||
|
|
|
|||
|
|
@ -18,7 +18,12 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c
|
|||
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
|
||||
ramstage-y += lan.c
|
||||
|
||||
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
|
||||
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c led.c
|
||||
|
||||
romstage-y += pei_data.c
|
||||
ramstage-y += pei_data.c
|
||||
romstage-y += variants/$(VARIANT_DIR)/pei_data.c
|
||||
ramstage-y += variants/$(VARIANT_DIR)/pei_data.c
|
||||
|
||||
romstage-y += led.c
|
||||
|
||||
subdirs-y += variants/$(VARIANT_DIR)
|
||||
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
|
||||
|
|
@ -1,82 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* This is board specific information: IRQ routing for IvyBridge */
|
||||
|
||||
// PCI Interrupt Routing
|
||||
Method(_PRT)
|
||||
{
|
||||
If (PICM) {
|
||||
Return (Package() {
|
||||
// Onboard graphics (IGD) 0:2.0
|
||||
Package() { 0x0002ffff, 0, 0, 16 },
|
||||
// Mini-HD Audio 0:3.0
|
||||
Package() { 0x0003ffff, 0, 0, 16 },
|
||||
// High Definition Audio 0:1b.0
|
||||
Package() { 0x001bffff, 0, 0, 22 },
|
||||
// PCIe Root Ports 0:1c.x
|
||||
Package() { 0x001cffff, 0, 0, 16 },
|
||||
Package() { 0x001cffff, 1, 0, 17 },
|
||||
Package() { 0x001cffff, 2, 0, 18 },
|
||||
Package() { 0x001cffff, 3, 0, 19 },
|
||||
// EHCI 0:1d.0
|
||||
Package() { 0x001dffff, 0, 0, 19 },
|
||||
// XHCI 0:14.0
|
||||
Package() { 0x0014ffff, 0, 0, 18 },
|
||||
// LPC devices 0:1f.0
|
||||
Package() { 0x001fffff, 0, 0, 22 },
|
||||
Package() { 0x001fffff, 1, 0, 18 },
|
||||
Package() { 0x001fffff, 2, 0, 17 },
|
||||
Package() { 0x001fffff, 3, 0, 16 },
|
||||
// Serial IO 0:15.0
|
||||
Package() { 0x0015ffff, 0, 0, 20 },
|
||||
Package() { 0x0015ffff, 1, 0, 21 },
|
||||
Package() { 0x0015ffff, 2, 0, 21 },
|
||||
Package() { 0x0015ffff, 3, 0, 21 },
|
||||
// SDIO 0:17.0
|
||||
Package() { 0x0017ffff, 0, 0, 23 },
|
||||
})
|
||||
} Else {
|
||||
Return (Package() {
|
||||
// Onboard graphics (IGD) 0:2.0
|
||||
Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
|
||||
// Mini-HD Audio 0:3.0
|
||||
Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
|
||||
// High Definition Audio 0:1b.0
|
||||
Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
|
||||
// PCIe Root Ports 0:1c.x
|
||||
Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
|
||||
Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
|
||||
Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
|
||||
Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
|
||||
// EHCI 0:1d.0
|
||||
Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
|
||||
// XHCI 0:14.0
|
||||
Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
|
||||
// LPC device 0:1f.0
|
||||
Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
|
||||
Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
|
||||
Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
|
||||
Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
|
||||
// Serial IO 0:15.0
|
||||
Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
|
||||
Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
|
||||
Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 },
|
||||
Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 },
|
||||
// SDIO 0:17.0
|
||||
Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
|
||||
})
|
||||
}
|
||||
}
|
||||
|
|
@ -24,14 +24,6 @@ Scope (\_SB)
|
|||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* LPC Trusted Platform Module
|
||||
*/
|
||||
Scope (\_SB.PCI0.LPCB)
|
||||
{
|
||||
#include <drivers/pc80/tpm/acpi/tpm.asl>
|
||||
}
|
||||
|
||||
/*
|
||||
* LAN connected to Root Port 3, becomes Root Port 1 after coalesce
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -26,7 +26,17 @@
|
|||
#include <device/pci_ids.h>
|
||||
#include <soc/acpi.h>
|
||||
#include <soc/nvs.h>
|
||||
#include "thermal.h"
|
||||
#include <variant/thermal.h>
|
||||
|
||||
|
||||
static void acpi_update_thermal_table(global_nvs_t *gnvs)
|
||||
{
|
||||
gnvs->tmps = TEMPERATURE_SENSOR_ID;
|
||||
gnvs->tcrt = CRITICAL_TEMPERATURE;
|
||||
gnvs->tpsv = PASSIVE_TEMPERATURE;
|
||||
gnvs->tmax = MAX_TEMPERATURE;
|
||||
gnvs->flvl = 1;
|
||||
}
|
||||
|
||||
void acpi_create_gnvs(global_nvs_t *gnvs)
|
||||
{
|
||||
|
|
@ -38,10 +48,7 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
|
|||
/* Disable USB ports in S5 */
|
||||
gnvs->s5u0 = 0;
|
||||
|
||||
gnvs->tmps = TEMPERATURE_SENSOR_ID;
|
||||
gnvs->tcrt = CRITICAL_TEMPERATURE;
|
||||
gnvs->tpsv = PASSIVE_TEMPERATURE;
|
||||
gnvs->tmax = MAX_TEMPERATURE;
|
||||
acpi_update_thermal_table(gnvs);
|
||||
}
|
||||
|
||||
unsigned long acpi_fill_madt(unsigned long current)
|
||||
|
|
|
|||
|
|
@ -9,9 +9,6 @@ chip soc/intel/broadwell
|
|||
# Enable HDMI Hotplug with 6ms pulse
|
||||
register "gpu_dp_b_hotplug" = "0x06"
|
||||
|
||||
|
||||
|
||||
|
||||
register "pirqa_routing" = "0x8b"
|
||||
register "pirqb_routing" = "0x8a"
|
||||
register "pirqc_routing" = "0x8b"
|
||||
|
|
@ -84,8 +81,14 @@ chip soc/intel/broadwell
|
|||
register "skip_keyboard" = "1"
|
||||
# Enable PECI on TMPIN3
|
||||
register "peci_tmpin" = "3"
|
||||
# Disable use of TMPIN1
|
||||
register "tmpin1_mode" = "0"
|
||||
# Enable Thermal Diode on TMPIN2
|
||||
register "tmpin2_mode" = "1"
|
||||
# Enable FAN2
|
||||
register "fan2_enable" = "1"
|
||||
# Default FAN2 speed
|
||||
register "fan2_speed" = "0x4d"
|
||||
|
||||
device pnp 2e.0 off end # FDC
|
||||
device pnp 2e.1 on # Serial Port 1
|
||||
|
|
|
|||
|
|
@ -44,7 +44,7 @@ DefinitionBlock(
|
|||
}
|
||||
|
||||
// Thermal handler
|
||||
#include "acpi/thermal.asl"
|
||||
#include <variant/acpi/thermal.asl>
|
||||
|
||||
// Chrome OS specific
|
||||
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
|
||||
|
|
|
|||
|
|
@ -15,21 +15,16 @@
|
|||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include <device/pci.h>
|
||||
#include <soc/acpi.h>
|
||||
#include <cpu/x86/smm.h>
|
||||
#include <soc/pch.h>
|
||||
#include <soc/iomap.h>
|
||||
|
||||
void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
|
||||
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
|
||||
{
|
||||
acpi_header_t *header = &(fadt->header);
|
||||
u16 pmbase = ACPI_BASE_ADDRESS;
|
||||
|
||||
memset((void *) fadt, 0, sizeof(acpi_fadt_t));
|
||||
memcpy(header->signature, "FACP", 4);
|
||||
header->length = sizeof(acpi_fadt_t);
|
||||
header->revision = 5;
|
||||
header->revision = 3;
|
||||
memcpy(header->oem_id, OEM_ID, 6);
|
||||
memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
|
||||
memcpy(header->asl_compiler_id, ASLC, 4);
|
||||
|
|
@ -40,114 +35,12 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
|
|||
fadt->model = 1;
|
||||
fadt->preferred_pm_profile = PM_MOBILE;
|
||||
|
||||
fadt->sci_int = 0x9;
|
||||
fadt->smi_cmd = APM_CNT;
|
||||
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
|
||||
fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
|
||||
fadt->s4bios_req = 0x0;
|
||||
fadt->pstate_cnt = 0;
|
||||
|
||||
fadt->pm1a_evt_blk = pmbase;
|
||||
fadt->pm1b_evt_blk = 0x0;
|
||||
fadt->pm1a_cnt_blk = pmbase + 0x4;
|
||||
fadt->pm1b_cnt_blk = 0x0;
|
||||
fadt->pm2_cnt_blk = pmbase + 0x50;
|
||||
fadt->pm_tmr_blk = pmbase + 0x8;
|
||||
fadt->gpe0_blk = pmbase + 0x80;
|
||||
fadt->gpe1_blk = 0;
|
||||
|
||||
fadt->pm1_evt_len = 4;
|
||||
fadt->pm1_cnt_len = 2;
|
||||
fadt->pm2_cnt_len = 1;
|
||||
fadt->pm_tmr_len = 4;
|
||||
fadt->gpe0_blk_len = 32;
|
||||
fadt->gpe1_blk_len = 0;
|
||||
fadt->gpe1_base = 0;
|
||||
fadt->cst_cnt = 0;
|
||||
fadt->p_lvl2_lat = 1;
|
||||
fadt->p_lvl3_lat = 87;
|
||||
fadt->flush_size = 1024;
|
||||
fadt->flush_stride = 16;
|
||||
fadt->duty_offset = 1;
|
||||
fadt->duty_width = 0;
|
||||
fadt->day_alrm = 0xd;
|
||||
fadt->mon_alrm = 0x00;
|
||||
fadt->century = 0x00;
|
||||
fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
|
||||
|
||||
fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
|
||||
ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
|
||||
ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |
|
||||
ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
|
||||
|
||||
fadt->reset_reg.space_id = 1;
|
||||
fadt->reset_reg.bit_width = 8;
|
||||
fadt->reset_reg.bit_offset = 0;
|
||||
fadt->reset_reg.resv = 0;
|
||||
fadt->reset_reg.addrl = 0xcf9;
|
||||
fadt->reset_reg.addrh = 0;
|
||||
|
||||
fadt->reset_value = 6;
|
||||
fadt->x_firmware_ctl_l = (unsigned long)facs;
|
||||
fadt->x_firmware_ctl_h = 0;
|
||||
fadt->x_dsdt_l = (unsigned long)dsdt;
|
||||
fadt->x_dsdt_h = 0;
|
||||
|
||||
fadt->x_pm1a_evt_blk.space_id = 1;
|
||||
fadt->x_pm1a_evt_blk.bit_width = 32;
|
||||
fadt->x_pm1a_evt_blk.bit_offset = 0;
|
||||
fadt->x_pm1a_evt_blk.resv = 0;
|
||||
fadt->x_pm1a_evt_blk.addrl = pmbase;
|
||||
fadt->x_pm1a_evt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1b_evt_blk.space_id = 1;
|
||||
fadt->x_pm1b_evt_blk.bit_width = 0;
|
||||
fadt->x_pm1b_evt_blk.bit_offset = 0;
|
||||
fadt->x_pm1b_evt_blk.resv = 0;
|
||||
fadt->x_pm1b_evt_blk.addrl = 0x0;
|
||||
fadt->x_pm1b_evt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1a_cnt_blk.space_id = 1;
|
||||
fadt->x_pm1a_cnt_blk.bit_width = 16;
|
||||
fadt->x_pm1a_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm1a_cnt_blk.resv = 0;
|
||||
fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
|
||||
fadt->x_pm1a_cnt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1b_cnt_blk.space_id = 1;
|
||||
fadt->x_pm1b_cnt_blk.bit_width = 0;
|
||||
fadt->x_pm1b_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm1b_cnt_blk.resv = 0;
|
||||
fadt->x_pm1b_cnt_blk.addrl = 0x0;
|
||||
fadt->x_pm1b_cnt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm2_cnt_blk.space_id = 1;
|
||||
fadt->x_pm2_cnt_blk.bit_width = 8;
|
||||
fadt->x_pm2_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm2_cnt_blk.resv = 0;
|
||||
fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
|
||||
fadt->x_pm2_cnt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm_tmr_blk.space_id = 1;
|
||||
fadt->x_pm_tmr_blk.bit_width = 32;
|
||||
fadt->x_pm_tmr_blk.bit_offset = 0;
|
||||
fadt->x_pm_tmr_blk.resv = 0;
|
||||
fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
|
||||
fadt->x_pm_tmr_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_gpe0_blk.space_id = 0;
|
||||
fadt->x_gpe0_blk.bit_width = 0;
|
||||
fadt->x_gpe0_blk.bit_offset = 0;
|
||||
fadt->x_gpe0_blk.resv = 0;
|
||||
fadt->x_gpe0_blk.addrl = 0;
|
||||
fadt->x_gpe0_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_gpe1_blk.space_id = 1;
|
||||
fadt->x_gpe1_blk.bit_width = 0;
|
||||
fadt->x_gpe1_blk.bit_offset = 0;
|
||||
fadt->x_gpe1_blk.resv = 0;
|
||||
fadt->x_gpe1_blk.addrl = 0x0;
|
||||
fadt->x_gpe1_blk.addrh = 0x0;
|
||||
acpi_fill_in_fadt(fadt);
|
||||
|
||||
header->checksum =
|
||||
acpi_checksum((void *) fadt, header->length);
|
||||
|
|
|
|||
|
|
@ -19,75 +19,59 @@ const u32 cim_verb_data[] = {
|
|||
/* coreboot specific header */
|
||||
0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283
|
||||
0x10ec0283, // Subsystem ID
|
||||
0x0000000c, // Number of jacks (NID entries)
|
||||
0x0000000e, // Number of jacks (NID entries)
|
||||
|
||||
/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10ec0283 */
|
||||
0x00172083,
|
||||
0x00172102,
|
||||
0x001722ec,
|
||||
0x00172310,
|
||||
0x0017ff00, // Function Reset
|
||||
0x0017ff00, // Double Function Reset
|
||||
0x000F0000, // Pad - get vendor id
|
||||
0x000F0002, // Pad - get revision id
|
||||
|
||||
/* NID 0x01, HDA Codec Subsystem ID Verb Table */
|
||||
AZALIA_SUBVENDOR(0x0, 0x11790670),
|
||||
|
||||
/* Pin Widget Verb Table */
|
||||
|
||||
/* Pin Complex (NID 0x12) DMIC */
|
||||
0x01271cf0,
|
||||
0x01271d11,
|
||||
0x01271e11,
|
||||
0x01271f41,
|
||||
/* Pin Complex (NID 0x12) DMIC - Disabled */
|
||||
AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0),
|
||||
|
||||
/* Pin Complex (NID 0x14) SPKR-OUT PORTD */
|
||||
0x01471cf0,
|
||||
0x01471d11,
|
||||
0x01471e11,
|
||||
0x01471f40,
|
||||
/* Pin Complex (NID 0x14) SPKR-OUT PORTD - Disabled */
|
||||
AZALIA_PIN_CFG(0x0, 0x14, 0x411111f0),
|
||||
|
||||
/* Pin Complex (NID 0x17) */
|
||||
0x01771cf0,
|
||||
0x01771d11,
|
||||
0x01771e11,
|
||||
0x01771f41,
|
||||
/* Pin Complex (NID 0x17) MONO Out - Disabled */
|
||||
AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0),
|
||||
|
||||
/* Pin Complex (NID 0x18) MIC1 PORTB */
|
||||
0x01971c11, // group 1, cap 1
|
||||
0x01971d10, // black, jack detect
|
||||
0x01971ea7, // mic in, analog
|
||||
0x01971f03, // connector, left panel
|
||||
// group 1, cap 1
|
||||
// black, jack detect
|
||||
// mic in, analog
|
||||
// connector, left panel
|
||||
AZALIA_PIN_CFG(0x0, 0x18, 0x03a71011),
|
||||
|
||||
/* Pin Complex (NID 0x19) MIC2 PORTF */
|
||||
0x01871cf0,
|
||||
0x01871d11,
|
||||
0x01871e11,
|
||||
0x01871f41,
|
||||
/* Pin Complex (NID 0x19) MIC2 PORTF - Disabled */
|
||||
AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0),
|
||||
|
||||
/* Pin Complex (NID 0x1A) LINE1 PORTC */
|
||||
0x01a71cf0,
|
||||
0x01a71d11,
|
||||
0x01a71e11,
|
||||
0x01a71f41,
|
||||
/* Pin Complex (NID 0x1A) LINE1 PORTC - Disabled */
|
||||
AZALIA_PIN_CFG(0x0, 0x1A, 0x411111f0),
|
||||
|
||||
/* Pin Complex (NID 0x1B) LINE2 PORTE */
|
||||
0x01a71cf0,
|
||||
0x01a71d11,
|
||||
0x01a71e11,
|
||||
0x01a71f41,
|
||||
/* Pin Complex (NID 0x1B) LINE2 PORTE - Disabled */
|
||||
AZALIA_PIN_CFG(0x0, 0x1B, 0x411111f0),
|
||||
|
||||
/* Pin Complex (NID 0x1d) PCBeep */
|
||||
0x01d71c2d, // eapd low on ex-amp, laptop, custom enable
|
||||
0x01d71d81, // mute spkr on hpout
|
||||
0x01d71e15, // pcbeep en able, checksum
|
||||
0x01d71f40, // no physical, internal
|
||||
/* Pin Complex (NID 0x1D) PCBeep */
|
||||
// eapd low on ex-amp, laptop, custom enable
|
||||
// mute spkr on hpout
|
||||
// pcbeep en able, checksum
|
||||
// no physical, internal
|
||||
AZALIA_PIN_CFG(0x0, 0x1D, 0x4015812d),
|
||||
|
||||
/* Pin Complex (NID 0x1E) SPDIF-OUT */
|
||||
0x01e71cf0,
|
||||
0x01e71d11,
|
||||
0x01e71e11,
|
||||
0x01e71f41,
|
||||
/* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled */
|
||||
AZALIA_PIN_CFG(0x0, 0x1E, 0x411111f0),
|
||||
|
||||
/* Pin Complex (NID 0x21) HPOUT PORT-I */
|
||||
0x02171c1f, // group1,
|
||||
0x02171d10, // black, jack detect
|
||||
0x02171e21, // HPOut, 1/8 stereo
|
||||
0x02171f03, // connector, left panel
|
||||
// group1,
|
||||
// black, jack detect
|
||||
// HPOut, 1/8 stereo
|
||||
// connector, left panel
|
||||
AZALIA_PIN_CFG(0x0, 0x21, 0x0321101f),
|
||||
|
||||
/* Undocumented settings from Realtek (needed for beep_gen) */
|
||||
/* Widget node 0x20 */
|
||||
|
|
@ -95,6 +79,12 @@ const u32 cim_verb_data[] = {
|
|||
0x02040c20,
|
||||
0x0205001b,
|
||||
0x0204081b,
|
||||
|
||||
/* Tuned jack detection */
|
||||
0x02050043,
|
||||
0x0204A614,
|
||||
0x02050047,
|
||||
0x02049470,
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <southbridge/intel/bd82x6x/pch.h>
|
||||
#include <soc/pch.h>
|
||||
#include "onboard.h"
|
||||
|
||||
static unsigned int search(char *p, u8 *a, unsigned int lengthp,
|
||||
|
|
|
|||
|
|
@ -14,22 +14,8 @@
|
|||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <types.h>
|
||||
#include <string.h>
|
||||
#include <smbios.h>
|
||||
#include <device/device.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <console/console.h>
|
||||
#if CONFIG_VGA_ROM_RUN
|
||||
#include <x86emu/x86emu.h>
|
||||
#endif
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/io.h>
|
||||
#include <arch/interrupt.h>
|
||||
#include <boot/coreboot_tables.h>
|
||||
#include <vendorcode/google/chromeos/chromeos.h>
|
||||
#include "onboard.h"
|
||||
|
||||
|
|
@ -39,92 +25,6 @@ void mainboard_suspend_resume(void)
|
|||
outb(0xcb, 0xb2);
|
||||
}
|
||||
|
||||
#if CONFIG_VGA_ROM_RUN
|
||||
static int int15_handler(void)
|
||||
{
|
||||
int res = 0;
|
||||
|
||||
printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
|
||||
__func__, X86_AX, X86_BX, X86_CX, X86_DX);
|
||||
|
||||
switch (X86_AX) {
|
||||
case 0x5f34:
|
||||
/*
|
||||
* Set Panel Fitting Hook:
|
||||
* bit 2 = Graphics Stretching
|
||||
* bit 1 = Text Stretching
|
||||
* bit 0 = Centering (do not set with bit1 or bit2)
|
||||
* 0 = video bios default
|
||||
*/
|
||||
X86_AX = 0x005f;
|
||||
X86_CX = 0x0001;
|
||||
res = 1;
|
||||
break;
|
||||
case 0x5f35:
|
||||
/*
|
||||
* Boot Display Device Hook:
|
||||
* bit 0 = CRT
|
||||
* bit 1 = TV (eDP) *
|
||||
* bit 2 = EFP *
|
||||
* bit 3 = LFP
|
||||
* bit 4 = CRT2
|
||||
* bit 5 = TV2 (eDP) *
|
||||
* bit 6 = EFP2 *
|
||||
* bit 7 = LFP2
|
||||
*/
|
||||
X86_AX = 0x005f;
|
||||
X86_CX = 0x0000;
|
||||
res = 1;
|
||||
break;
|
||||
case 0x5f51:
|
||||
/*
|
||||
* Hook to select active LFP configuration:
|
||||
* 00h = No LVDS, VBIOS does not enable LVDS
|
||||
* 01h = Int-LVDS, LFP driven by integrated LVDS decoder
|
||||
* 02h = SVDO-LVDS, LFP driven by SVDO decoder
|
||||
* 03h = eDP, LFP Driven by Int-DisplayPort encoder
|
||||
*/
|
||||
X86_AX = 0x005f;
|
||||
X86_CX = 0x0003;
|
||||
res = 1;
|
||||
break;
|
||||
case 0x5f70:
|
||||
switch ((X86_CX >> 8) & 0xff) {
|
||||
case 0:
|
||||
/* Get Mux */
|
||||
X86_AX = 0x005f;
|
||||
X86_CX = 0x0000;
|
||||
res = 1;
|
||||
break;
|
||||
case 1:
|
||||
/* Set Mux */
|
||||
X86_AX = 0x005f;
|
||||
X86_CX = 0x0000;
|
||||
res = 1;
|
||||
break;
|
||||
case 2:
|
||||
/* Get SG/Non-SG mode */
|
||||
X86_AX = 0x005f;
|
||||
X86_CX = 0x0000;
|
||||
res = 1;
|
||||
break;
|
||||
default:
|
||||
/* Interrupt was not handled */
|
||||
printk(BIOS_DEBUG,
|
||||
"Unknown INT15 5f70 function: 0x%02x\n",
|
||||
((X86_CX >> 8) & 0xff));
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX);
|
||||
break;
|
||||
}
|
||||
return res;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void mainboard_init(device_t dev)
|
||||
{
|
||||
lan_init();
|
||||
|
|
@ -137,10 +37,6 @@ static void mainboard_enable(device_t dev)
|
|||
{
|
||||
dev->ops->init = mainboard_init;
|
||||
dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
|
||||
#if CONFIG_VGA_ROM_RUN
|
||||
/* Install custom int15 handler for VGA OPROM */
|
||||
mainboard_interrupt_handlers(0x15, &int15_handler);
|
||||
#endif
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
|
|
|
|||
|
|
@ -18,6 +18,14 @@
|
|||
|
||||
#ifndef __ACPI__
|
||||
void lan_init(void);
|
||||
|
||||
void set_power_led(int state);
|
||||
|
||||
enum {
|
||||
LED_OFF = 0,
|
||||
LED_ON,
|
||||
LED_BLINK,
|
||||
};
|
||||
#endif
|
||||
|
||||
/* defines for programming the MAC address */
|
||||
|
|
@ -33,4 +41,13 @@ void lan_init(void);
|
|||
/* WLAN wake is GPIO 10 */
|
||||
#define JECHT_WLAN_WAKE_GPIO 10
|
||||
|
||||
/* USB Charger Control: GPIO26 */
|
||||
#define GPIO_USB_CTL_1 26
|
||||
|
||||
/* IT8772F defs */
|
||||
#define IT8772F_BASE 0x2e
|
||||
#define IT8772F_SERIAL_DEV PNP_DEV(IT8772F_BASE, IT8772F_SP1)
|
||||
#define IT8772F_GPIO_DEV PNP_DEV(IT8772F_BASE, IT8772F_GPIO)
|
||||
#define IT8772F_DUMMY_DEV PNP_DEV(IT8772F_BASE, 0)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -25,11 +25,9 @@
|
|||
#include <superio/ite/common/ite.h>
|
||||
#include <superio/ite/it8772f/it8772f.h>
|
||||
#include <mainboard/google/jecht/spd/spd.h>
|
||||
#include "gpio.h"
|
||||
#include <variant/gpio.h>
|
||||
#include "onboard.h"
|
||||
|
||||
#define DUMMY_DEV PNP_DEV(0x2e, 0)
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1)
|
||||
#define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO)
|
||||
|
||||
void mainboard_romstage_entry(struct romstage_params *rp)
|
||||
{
|
||||
|
|
@ -53,7 +51,11 @@ void mainboard_romstage_entry(struct romstage_params *rp)
|
|||
void mainboard_pre_console_init(void)
|
||||
{
|
||||
/* Early SuperIO setup */
|
||||
it8772f_ac_resume_southbridge(DUMMY_DEV);
|
||||
ite_kill_watchdog(GPIO_DEV);
|
||||
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
it8772f_ac_resume_southbridge(IT8772F_DUMMY_DEV);
|
||||
ite_kill_watchdog(IT8772F_GPIO_DEV);
|
||||
ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
|
||||
/* Turn On Power LED */
|
||||
set_power_led(LED_ON);
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -27,6 +27,7 @@
|
|||
#include <soc/nvs.h>
|
||||
#include <soc/pm.h>
|
||||
#include <soc/smm.h>
|
||||
#include "onboard.h"
|
||||
|
||||
int mainboard_io_trap_handler(int smif)
|
||||
{
|
||||
|
|
@ -58,8 +59,15 @@ void mainboard_smi_sleep(u8 slp_typ)
|
|||
/* Disable USB charging if required */
|
||||
switch (slp_typ) {
|
||||
case ACPI_S3:
|
||||
set_power_led(LED_BLINK);
|
||||
|
||||
/* Enable DCP mode */
|
||||
if (IS_ENABLED(CONFIG_BOARD_GOOGLE_TIDUS)) {
|
||||
set_gpio(GPIO_USB_CTL_1, 0);
|
||||
}
|
||||
break;
|
||||
case ACPI_S5:
|
||||
set_power_led(LED_OFF);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -13,13 +13,7 @@
|
|||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <cbfs.h>
|
||||
#include <console/console.h>
|
||||
#include <endian.h>
|
||||
#include <string.h>
|
||||
#include <soc/gpio.h>
|
||||
#include <soc/pei_data.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <mainboard/google/jecht/spd/spd.h>
|
||||
|
||||
/* Copy SPD data for on-board memory */
|
||||
|
|
|
|||
|
|
@ -154,9 +154,9 @@ Scope (\_TZ)
|
|||
|
||||
Method (_AC4) {
|
||||
If (LLessEqual (\FLVL, 4)) {
|
||||
Return (CTOK (FAN4_THRESHOLD_OFF))
|
||||
Return (CTOK (0))
|
||||
} Else {
|
||||
Return (CTOK (FAN4_THRESHOLD_ON))
|
||||
Return (CTOK (0))
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -18,10 +18,8 @@
|
|||
|
||||
#define TEMPERATURE_SENSOR_ID 0 /* PECI */
|
||||
|
||||
/* Fan is OFF */
|
||||
#define FAN4_THRESHOLD_OFF 0
|
||||
#define FAN4_THRESHOLD_ON 0
|
||||
#define FAN4_PWM 0x00
|
||||
/* Fan is at default speed */
|
||||
#define FAN4_PWM 0x4d
|
||||
|
||||
/* Fan is at LOW speed */
|
||||
#define FAN3_THRESHOLD_OFF 40
|
||||
|
|
@ -154,9 +154,9 @@ Scope (\_TZ)
|
|||
|
||||
Method (_AC4) {
|
||||
If (LLessEqual (\FLVL, 4)) {
|
||||
Return (CTOK (FAN4_THRESHOLD_OFF))
|
||||
Return (CTOK (0))
|
||||
} Else {
|
||||
Return (CTOK (FAN4_THRESHOLD_ON))
|
||||
Return (CTOK (0))
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -18,10 +18,8 @@
|
|||
|
||||
#define TEMPERATURE_SENSOR_ID 0 /* PECI */
|
||||
|
||||
/* Fan is OFF */
|
||||
#define FAN4_THRESHOLD_OFF 0
|
||||
#define FAN4_THRESHOLD_ON 0
|
||||
#define FAN4_PWM 0x00
|
||||
/* Fan is at default speed */
|
||||
#define FAN4_PWM 0x4d
|
||||
|
||||
/* Fan is at LOW speed */
|
||||
#define FAN3_THRESHOLD_OFF 50
|
||||
|
|
@ -154,9 +154,9 @@ Scope (\_TZ)
|
|||
|
||||
Method (_AC4) {
|
||||
If (LLessEqual (\FLVL, 4)) {
|
||||
Return (CTOK (FAN4_THRESHOLD_OFF))
|
||||
Return (CTOK (0))
|
||||
} Else {
|
||||
Return (CTOK (FAN4_THRESHOLD_ON))
|
||||
Return (CTOK (0))
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -18,10 +18,8 @@
|
|||
|
||||
#define TEMPERATURE_SENSOR_ID 0 /* PECI */
|
||||
|
||||
/* Fan is OFF */
|
||||
#define FAN4_THRESHOLD_OFF 0
|
||||
#define FAN4_THRESHOLD_ON 0
|
||||
#define FAN4_PWM 0x84
|
||||
/* Fan is at default speed */
|
||||
#define FAN4_PWM 0x4d
|
||||
|
||||
/* Fan is at LOW speed */
|
||||
#define FAN3_THRESHOLD_OFF 42
|
||||
|
|
@ -16,6 +16,8 @@
|
|||
#ifndef THERMAL_H
|
||||
#define THERMAL_H
|
||||
|
||||
#define TEMPERATURE_SENSOR_ID 0 /* PECI */
|
||||
|
||||
/* Thermal Policy 0 */
|
||||
/* Fan is at default speed */
|
||||
#define FAN4_0_PWM 0x4d
|
||||
|
|
@ -1,67 +0,0 @@
|
|||
if BOARD_GOOGLE_RIKKU
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
def_bool y
|
||||
select SOC_INTEL_BROADWELL
|
||||
select BOARD_ROMSIZE_KB_8192
|
||||
select SUPERIO_ITE_IT8772F
|
||||
select HAVE_ACPI_TABLES
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_ACPI_RESUME
|
||||
select HAVE_SMI_HANDLER
|
||||
select MAINBOARD_HAS_CHROMEOS
|
||||
select MAINBOARD_HAS_LPC_TPM
|
||||
|
||||
config CHROMEOS
|
||||
select CHROMEOS_RAMOOPS_DYNAMIC
|
||||
select PHYSICAL_REC_SWITCH
|
||||
select VBOOT_VBNV_CMOS
|
||||
select VIRTUAL_DEV_SWITCH
|
||||
|
||||
config VBOOT_RAMSTAGE_INDEX
|
||||
hex
|
||||
default 0x2
|
||||
|
||||
config VBOOT_REFCODE_INDEX
|
||||
hex
|
||||
default 0x3
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default google/rikku
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "Rikku"
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 18
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 8
|
||||
|
||||
config VGA_BIOS_FILE
|
||||
string
|
||||
default "pci8086,0166.rom"
|
||||
|
||||
config HAVE_IFD_BIN
|
||||
bool
|
||||
default n
|
||||
|
||||
config HAVE_ME_BIN
|
||||
bool
|
||||
default n
|
||||
|
||||
config MAINBOARD_FAMILY
|
||||
string
|
||||
depends on GENERATE_SMBIOS_TABLES
|
||||
default "Google_Rikku"
|
||||
|
||||
config GBB_HWID
|
||||
string
|
||||
depends on CHROMEOS
|
||||
default "RIKKU TEST A-A 0702"
|
||||
|
||||
endif
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
config BOARD_GOOGLE_RIKKU
|
||||
bool "Rikku"
|
||||
|
|
@ -1,24 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2015 Google Inc.
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
|
||||
subdirs-y += spd
|
||||
romstage-$(CONFIG_CHROMEOS) += chromeos.c
|
||||
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
|
||||
ramstage-y += lan.c
|
||||
|
||||
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
|
||||
|
||||
romstage-y += pei_data.c
|
||||
ramstage-y += pei_data.c
|
||||
|
|
@ -1,82 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* This is board specific information: IRQ routing for IvyBridge */
|
||||
|
||||
// PCI Interrupt Routing
|
||||
Method(_PRT)
|
||||
{
|
||||
If (PICM) {
|
||||
Return (Package() {
|
||||
// Onboard graphics (IGD) 0:2.0
|
||||
Package() { 0x0002ffff, 0, 0, 16 },
|
||||
// Mini-HD Audio 0:3.0
|
||||
Package() { 0x0003ffff, 0, 0, 16 },
|
||||
// High Definition Audio 0:1b.0
|
||||
Package() { 0x001bffff, 0, 0, 22 },
|
||||
// PCIe Root Ports 0:1c.x
|
||||
Package() { 0x001cffff, 0, 0, 16 },
|
||||
Package() { 0x001cffff, 1, 0, 17 },
|
||||
Package() { 0x001cffff, 2, 0, 18 },
|
||||
Package() { 0x001cffff, 3, 0, 19 },
|
||||
// EHCI 0:1d.0
|
||||
Package() { 0x001dffff, 0, 0, 19 },
|
||||
// XHCI 0:14.0
|
||||
Package() { 0x0014ffff, 0, 0, 18 },
|
||||
// LPC devices 0:1f.0
|
||||
Package() { 0x001fffff, 0, 0, 22 },
|
||||
Package() { 0x001fffff, 1, 0, 18 },
|
||||
Package() { 0x001fffff, 2, 0, 17 },
|
||||
Package() { 0x001fffff, 3, 0, 16 },
|
||||
// Serial IO 0:15.0
|
||||
Package() { 0x0015ffff, 0, 0, 20 },
|
||||
Package() { 0x0015ffff, 1, 0, 21 },
|
||||
Package() { 0x0015ffff, 2, 0, 21 },
|
||||
Package() { 0x0015ffff, 3, 0, 21 },
|
||||
// SDIO 0:17.0
|
||||
Package() { 0x0017ffff, 0, 0, 23 },
|
||||
})
|
||||
} Else {
|
||||
Return (Package() {
|
||||
// Onboard graphics (IGD) 0:2.0
|
||||
Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
|
||||
// Mini-HD Audio 0:3.0
|
||||
Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
|
||||
// High Definition Audio 0:1b.0
|
||||
Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
|
||||
// PCIe Root Ports 0:1c.x
|
||||
Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
|
||||
Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
|
||||
Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
|
||||
Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
|
||||
// EHCI 0:1d.0
|
||||
Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
|
||||
// XHCI 0:14.0
|
||||
Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
|
||||
// LPC device 0:1f.0
|
||||
Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
|
||||
Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
|
||||
Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
|
||||
Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
|
||||
// Serial IO 0:15.0
|
||||
Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
|
||||
Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
|
||||
Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 },
|
||||
Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 },
|
||||
// SDIO 0:17.0
|
||||
Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
|
||||
})
|
||||
}
|
||||
}
|
||||
|
|
@ -1,69 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <mainboard/google/rikku/onboard.h>
|
||||
|
||||
Scope (\_SB)
|
||||
{
|
||||
Device (PWRB)
|
||||
{
|
||||
Name(_HID, EisaId("PNP0C0C"))
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* LAN connected to Root Port 3, becomes Root Port 1 after coalesce
|
||||
*/
|
||||
Scope (\_SB.PCI0.RP01)
|
||||
{
|
||||
Device (ETH0)
|
||||
{
|
||||
Name (_ADR, 0x00000000)
|
||||
Name (_PRW, Package() { RIKKU_NIC_WAKE_GPIO, 3 })
|
||||
|
||||
Method (_DSW, 3, NotSerialized)
|
||||
{
|
||||
Store (RIKKU_NIC_WAKE_GPIO, Local0)
|
||||
|
||||
If (LEqual (Arg0, 1)) {
|
||||
// Enable GPIO as wake source
|
||||
\_SB.PCI0.LPCB.GPIO.GWAK (Local0)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* WLAN connected to Root Port 4, becomes Root Port 2 after coalesce
|
||||
*/
|
||||
Scope (\_SB.PCI0.RP02)
|
||||
{
|
||||
Device (WLAN)
|
||||
{
|
||||
Name (_ADR, 0x00000000)
|
||||
Name (_PRW, Package() { RIKKU_WLAN_WAKE_GPIO, 3 })
|
||||
|
||||
Method (_DSW, 3, NotSerialized)
|
||||
{
|
||||
Store (RIKKU_WLAN_WAKE_GPIO, Local0)
|
||||
|
||||
If (LEqual (Arg0, 1)) {
|
||||
// Enable GPIO as wake source
|
||||
\_SB.PCI0.LPCB.GPIO.GWAK (Local0)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,71 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2015 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* The APM port can be used for generating software SMIs */
|
||||
|
||||
OperationRegion (APMP, SystemIO, 0xb2, 2)
|
||||
Field (APMP, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
APMC, 8, // APM command
|
||||
APMS, 8 // APM status
|
||||
}
|
||||
|
||||
/* Port 80 POST */
|
||||
|
||||
OperationRegion (POST, SystemIO, 0x80, 1)
|
||||
Field (POST, ByteAcc, Lock, Preserve)
|
||||
{
|
||||
DBG0, 8
|
||||
}
|
||||
|
||||
/* SMI I/O Trap */
|
||||
Method(TRAP, 1, Serialized)
|
||||
{
|
||||
Store (Arg0, SMIF) // SMI Function
|
||||
Store (0, TRP0) // Generate trap
|
||||
Return (SMIF) // Return value of SMI handler
|
||||
}
|
||||
|
||||
/* The _PIC method is called by the OS to choose between interrupt
|
||||
* routing via the i8259 interrupt controller or the APIC.
|
||||
*
|
||||
* _PIC is called with a parameter of 0 for i8259 configuration and
|
||||
* with a parameter of 1 for Local Apic/IOAPIC configuration.
|
||||
*/
|
||||
|
||||
Method(_PIC, 1)
|
||||
{
|
||||
// Remember the OS' IRQ routing choice.
|
||||
Store(Arg0, PICM)
|
||||
}
|
||||
|
||||
/* The _PTS method (Prepare To Sleep) is called before the OS is
|
||||
* entering a sleep state. The sleep state number is passed in Arg0
|
||||
*/
|
||||
|
||||
Method(_PTS,1)
|
||||
{
|
||||
}
|
||||
|
||||
/* The _WAK method is called on system wakeup */
|
||||
|
||||
Method(_WAK,1)
|
||||
{
|
||||
/* Initialize thermal defaults */
|
||||
\_TZ.THRM._INI ()
|
||||
|
||||
Return(Package(){0,0})
|
||||
}
|
||||
|
|
@ -1,31 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* Values should match those defined in devicetree.cb */
|
||||
|
||||
#undef SIO_ENABLE_FDC0 // pnp 2e.0: Disable Floppy Controller
|
||||
#undef SIO_ENABLE_INFR // pnp 2e.a: Disable Consumer IR
|
||||
|
||||
#undef SIO_ENABLE_PS2K // pnp 2e.5: Disable PS/2 Keyboard
|
||||
#undef SIO_ENABLE_PS2M // pnp 2e.6: Disable PS/2 Mouse
|
||||
#define SIO_ENABLE_COM1 // pnp 2e.1: Enable Serial Port 1
|
||||
#define SIO_ENABLE_ENVC // pnp 2e.4: Enable Environmental Controller
|
||||
#define SIO_ENVC_IO0 0x700 // pnp 2e.4: io 0x60
|
||||
#define SIO_ENVC_IO1 0x710 // pnp 2e.4: io 0x62
|
||||
#define SIO_ENABLE_GPIO // pnp 2e.7: Enable GPIO
|
||||
#define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60
|
||||
#define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60
|
||||
|
||||
#include "superio/ite/it8772f/acpi/superio.asl"
|
||||
|
|
@ -1,38 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
// Brightness write
|
||||
Method (BRTW, 1, Serialized)
|
||||
{
|
||||
// TODO
|
||||
}
|
||||
|
||||
// Hot Key Display Switch
|
||||
Method (HKDS, 1, Serialized)
|
||||
{
|
||||
// TODO
|
||||
}
|
||||
|
||||
// Lid Switch Display Switch
|
||||
Method (LSDS, 1, Serialized)
|
||||
{
|
||||
// TODO
|
||||
}
|
||||
|
||||
// Brightness Notification
|
||||
Method(BRTN,1,Serialized)
|
||||
{
|
||||
// TODO (no displays defined yet)
|
||||
}
|
||||
|
|
@ -1,65 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <types.h>
|
||||
#include <string.h>
|
||||
#include <cbmem.h>
|
||||
#include <console/console.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <arch/acpigen.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <soc/acpi.h>
|
||||
#include <soc/nvs.h>
|
||||
#include "thermal.h"
|
||||
|
||||
|
||||
static void acpi_update_thermal_table(global_nvs_t *gnvs)
|
||||
{
|
||||
gnvs->tmps = TEMPERATURE_SENSOR_ID;
|
||||
|
||||
gnvs->tcrt = CRITICAL_TEMPERATURE;
|
||||
gnvs->tpsv = PASSIVE_TEMPERATURE;
|
||||
gnvs->tmax = MAX_TEMPERATURE;
|
||||
gnvs->flvl = 1;
|
||||
}
|
||||
|
||||
void acpi_create_gnvs(global_nvs_t *gnvs)
|
||||
{
|
||||
acpi_init_gnvs(gnvs);
|
||||
|
||||
/* Enable USB ports in S3 */
|
||||
gnvs->s3u0 = 1;
|
||||
|
||||
/* Disable USB ports in S5 */
|
||||
gnvs->s5u0 = 0;
|
||||
|
||||
acpi_update_thermal_table(gnvs);
|
||||
}
|
||||
|
||||
unsigned long acpi_fill_madt(unsigned long current)
|
||||
{
|
||||
/* Local APICs */
|
||||
current = acpi_create_madt_lapics(current);
|
||||
|
||||
/* IOAPIC */
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
|
||||
2, IO_APIC_ADDR, 0);
|
||||
|
||||
return acpi_madt_irq_overrides(current);
|
||||
}
|
||||
|
|
@ -1,7 +0,0 @@
|
|||
Vendor name: Acer
|
||||
Board name: Chromebox CXI2
|
||||
Category: half
|
||||
ROM package: SOIC-8
|
||||
ROM protocol: SPI
|
||||
ROM socketed: n
|
||||
Flashrom support: y
|
||||
|
|
@ -1,105 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <console/console.h>
|
||||
#include <vendorcode/google/chromeos/chromeos.h>
|
||||
#include <ec/google/chromeec/ec.h>
|
||||
#include <soc/gpio.h>
|
||||
#include <soc/sata.h>
|
||||
|
||||
#define GPIO_SPI_WP 58
|
||||
#define GPIO_REC_MODE 12
|
||||
|
||||
#define FLAG_SPI_WP 0
|
||||
#define FLAG_REC_MODE 1
|
||||
#define FLAG_DEV_MODE 2
|
||||
|
||||
#ifndef __PRE_RAM__
|
||||
#include <boot/coreboot_tables.h>
|
||||
|
||||
void fill_lb_gpios(struct lb_gpios *gpios)
|
||||
{
|
||||
struct lb_gpio chromeos_gpios[] = {
|
||||
{GPIO_SPI_WP, ACTIVE_HIGH, 0, "write protect"},
|
||||
{GPIO_REC_MODE, ACTIVE_LOW,
|
||||
get_recovery_mode_switch(), "recovery"},
|
||||
{-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"},
|
||||
{-1, ACTIVE_HIGH, 1, "lid"},
|
||||
{-1, ACTIVE_HIGH, 0, "power"},
|
||||
{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
|
||||
};
|
||||
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
|
||||
}
|
||||
#endif
|
||||
|
||||
int get_write_protect_state(void)
|
||||
{
|
||||
device_t dev;
|
||||
#ifdef __PRE_RAM__
|
||||
dev = PCI_DEV(0, 0x1f, 2);
|
||||
#else
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
|
||||
#endif
|
||||
return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;
|
||||
}
|
||||
|
||||
int get_developer_mode_switch(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int get_recovery_mode_switch(void)
|
||||
{
|
||||
device_t dev;
|
||||
#ifdef __PRE_RAM__
|
||||
dev = PCI_DEV(0, 0x1f, 2);
|
||||
#else
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
|
||||
#endif
|
||||
return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;
|
||||
}
|
||||
|
||||
#ifdef __PRE_RAM__
|
||||
void save_chromeos_gpios(void)
|
||||
{
|
||||
u32 flags = 0;
|
||||
|
||||
/* Write Protect: GPIO58 = GPIO_SPI_WP, active high */
|
||||
if (get_gpio(GPIO_SPI_WP))
|
||||
flags |= (1 << FLAG_SPI_WP);
|
||||
|
||||
/* Recovery: GPIO12 = RECOVERY_L, active low */
|
||||
if (!get_gpio(GPIO_REC_MODE))
|
||||
flags |= (1 << FLAG_REC_MODE);
|
||||
|
||||
/* Developer: Virtual */
|
||||
|
||||
pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags);
|
||||
}
|
||||
#endif
|
||||
|
||||
static const struct cros_gpio cros_gpios[] = {
|
||||
CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME),
|
||||
CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
|
||||
};
|
||||
|
||||
void mainboard_chromeos_acpi_generate(void)
|
||||
{
|
||||
chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
|
||||
}
|
||||
|
|
@ -1,38 +0,0 @@
|
|||
FLASH@0xff800000 0x800000 {
|
||||
SI_ALL@0x0 0x200000 {
|
||||
SI_DESC@0x0 0x1000
|
||||
SI_ME@0x1000 0x1ff000
|
||||
}
|
||||
SI_BIOS@0x200000 0x600000 {
|
||||
RW_SECTION_A@0x0 0xf0000 {
|
||||
VBLOCK_A@0x0 0x10000
|
||||
FW_MAIN_A(CBFS)@0x10000 0xdffc0
|
||||
RW_FWID_A@0xeffc0 0x40
|
||||
}
|
||||
RW_SECTION_B@0xf0000 0xf0000 {
|
||||
VBLOCK_B@0x0 0x10000
|
||||
FW_MAIN_B(CBFS)@0x10000 0xdffc0
|
||||
RW_FWID_B@0xeffc0 0x40
|
||||
}
|
||||
RW_MRC_CACHE@0x1e0000 0x10000
|
||||
RW_ELOG@0x1f0000 0x4000
|
||||
RW_SHARED@0x1f4000 0x4000 {
|
||||
SHARED_DATA@0x0 0x2000
|
||||
VBLOCK_DEV@0x2000 0x2000
|
||||
}
|
||||
RW_VPD@0x1f8000 0x2000
|
||||
RW_UNUSED@0x1fa000 0x6000
|
||||
RW_LEGACY(CBFS)@0x200000 0x200000
|
||||
WP_RO@0x400000 0x200000 {
|
||||
RO_VPD@0x0 0x4000
|
||||
RO_UNUSED@0x4000 0xc000
|
||||
RO_SECTION@0x10000 0x1f0000 {
|
||||
FMAP@0x0 0x800
|
||||
RO_FRID@0x800 0x40
|
||||
RO_FRID_PAD@0x840 0x7c0
|
||||
GBB@0x1000 0xef000
|
||||
COREBOOT(CBFS)@0xf0000 0x100000
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,132 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007-2008 coresystems GmbH
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
entries
|
||||
|
||||
#start-bit length config config-ID name
|
||||
#0 8 r 0 seconds
|
||||
#8 8 r 0 alarm_seconds
|
||||
#16 8 r 0 minutes
|
||||
#24 8 r 0 alarm_minutes
|
||||
#32 8 r 0 hours
|
||||
#40 8 r 0 alarm_hours
|
||||
#48 8 r 0 day_of_week
|
||||
#56 8 r 0 day_of_month
|
||||
#64 8 r 0 month
|
||||
#72 8 r 0 year
|
||||
# -----------------------------------------------------------------
|
||||
# Status Register A
|
||||
#80 4 r 0 rate_select
|
||||
#84 3 r 0 REF_Clock
|
||||
#87 1 r 0 UIP
|
||||
# -----------------------------------------------------------------
|
||||
# Status Register B
|
||||
#88 1 r 0 auto_switch_DST
|
||||
#89 1 r 0 24_hour_mode
|
||||
#90 1 r 0 binary_values_enable
|
||||
#91 1 r 0 square-wave_out_enable
|
||||
#92 1 r 0 update_finished_enable
|
||||
#93 1 r 0 alarm_interrupt_enable
|
||||
#94 1 r 0 periodic_interrupt_enable
|
||||
#95 1 r 0 disable_clock_updates
|
||||
# -----------------------------------------------------------------
|
||||
# Status Register C
|
||||
#96 4 r 0 status_c_rsvd
|
||||
#100 1 r 0 uf_flag
|
||||
#101 1 r 0 af_flag
|
||||
#102 1 r 0 pf_flag
|
||||
#103 1 r 0 irqf_flag
|
||||
# -----------------------------------------------------------------
|
||||
# Status Register D
|
||||
#104 7 r 0 status_d_rsvd
|
||||
#111 1 r 0 valid_cmos_ram
|
||||
# -----------------------------------------------------------------
|
||||
# Diagnostic Status Register
|
||||
#112 8 r 0 diag_rsvd1
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
0 120 r 0 reserved_memory
|
||||
#120 264 r 0 unused
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||
384 1 e 4 boot_option
|
||||
388 4 h 0 reboot_counter
|
||||
#390 2 r 0 unused?
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
# coreboot config options: console
|
||||
392 3 e 5 baud_rate
|
||||
395 4 e 6 debug_level
|
||||
#399 1 r 0 unused
|
||||
|
||||
# coreboot config options: cpu
|
||||
400 1 e 2 hyper_threading
|
||||
#401 7 r 0 unused
|
||||
|
||||
# coreboot config options: southbridge
|
||||
408 1 e 1 nmi
|
||||
409 2 e 7 power_on_after_fail
|
||||
#411 5 r 0 unused
|
||||
|
||||
# coreboot config options: bootloader
|
||||
#Used by ChromeOS:
|
||||
416 128 r 0 vbnv
|
||||
#544 440 r 0 unused
|
||||
|
||||
# SandyBridge MRC Scrambler Seed values
|
||||
896 32 r 0 mrc_scrambler_seed
|
||||
928 32 r 0 mrc_scrambler_seed_s3
|
||||
|
||||
# coreboot config options: check sums
|
||||
984 16 h 0 check_sum
|
||||
#1000 24 r 0 amd_reserved
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
5 0 115200
|
||||
5 1 57600
|
||||
5 2 38400
|
||||
5 3 19200
|
||||
5 4 9600
|
||||
5 5 4800
|
||||
5 6 2400
|
||||
5 7 1200
|
||||
6 1 Emergency
|
||||
6 2 Alert
|
||||
6 3 Critical
|
||||
6 4 Error
|
||||
6 5 Warning
|
||||
6 6 Notice
|
||||
6 7 Info
|
||||
6 8 Debug
|
||||
6 9 Spew
|
||||
7 0 Disable
|
||||
7 1 Enable
|
||||
7 2 Keep
|
||||
# -----------------------------------------------------------------
|
||||
checksums
|
||||
|
||||
checksum 392 415 984
|
||||
|
|
@ -1,119 +0,0 @@
|
|||
chip soc/intel/broadwell
|
||||
|
||||
# Disable eDP Hotplug
|
||||
register "gpu_dp_d_hotplug" = "0x00"
|
||||
|
||||
# Enable DisplayPort C Hotplug with 6ms pulse
|
||||
register "gpu_dp_c_hotplug" = "0x06"
|
||||
|
||||
# Enable HDMI Hotplug with 6ms pulse
|
||||
register "gpu_dp_b_hotplug" = "0x06"
|
||||
|
||||
register "pirqa_routing" = "0x8b"
|
||||
register "pirqb_routing" = "0x8a"
|
||||
register "pirqc_routing" = "0x8b"
|
||||
register "pirqd_routing" = "0x8b"
|
||||
register "pirqe_routing" = "0x80"
|
||||
register "pirqf_routing" = "0x80"
|
||||
register "pirqg_routing" = "0x80"
|
||||
register "pirqh_routing" = "0x80"
|
||||
|
||||
# SuperIO range is 0x700-0x73f
|
||||
register "gen2_dec" = "0x003c0701"
|
||||
|
||||
register "alt_gp_smi_en" = "0x0000"
|
||||
register "gpe0_en_1" = "0x00000000"
|
||||
register "gpe0_en_2" = "0x00000000"
|
||||
register "gpe0_en_3" = "0x00000000"
|
||||
register "gpe0_en_4" = "0x00000000"
|
||||
|
||||
register "sata_port_map" = "0x1"
|
||||
register "sata_devslp_disable" = "0x1"
|
||||
|
||||
register "sio_acpi_mode" = "0"
|
||||
register "sio_i2c0_voltage" = "0" # 3.3V
|
||||
register "sio_i2c1_voltage" = "0" # 3.3V
|
||||
|
||||
# Force enable ASPM for PCIe Port 4
|
||||
register "pcie_port_force_aspm" = "0x10"
|
||||
|
||||
# Enable port coalescing
|
||||
register "pcie_port_coalesce" = "1"
|
||||
|
||||
# Disable PCIe CLKOUT 1,5 and CLKOUT_XDP
|
||||
register "icc_clock_disable" = "0x01220000"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # host bridge
|
||||
device pci 02.0 on end # vga controller
|
||||
device pci 03.0 on end # mini-hd audio
|
||||
device pci 13.0 off end # Smart Sound Audio DSP
|
||||
device pci 14.0 on end # USB3 XHCI
|
||||
device pci 15.0 off end # Serial I/O DMA
|
||||
device pci 15.1 off end # I2C0
|
||||
device pci 15.2 off end # I2C1
|
||||
device pci 15.3 off end # GSPI0
|
||||
device pci 15.4 off end # GSPI1
|
||||
device pci 15.5 off end # UART0
|
||||
device pci 15.6 off end # UART1
|
||||
device pci 16.0 on end # Management Engine Interface 1
|
||||
device pci 16.1 off end # Management Engine Interface 2
|
||||
device pci 16.2 off end # Management Engine IDE-R
|
||||
device pci 16.3 off end # Management Engine KT
|
||||
device pci 17.0 off end # SDIO
|
||||
device pci 19.0 off end # GbE
|
||||
device pci 1b.0 on end # High Definition Audio
|
||||
device pci 1c.0 off end # PCIe Port #1
|
||||
device pci 1c.1 off end # PCIe Port #2
|
||||
device pci 1c.2 on end # PCIe Port #3
|
||||
device pci 1c.3 on end # PCIe Port #4
|
||||
device pci 1c.4 on end # PCIe Port #5
|
||||
device pci 1c.5 off end # PCIe Port #6
|
||||
device pci 1d.0 on end # USB2 EHCI
|
||||
device pci 1e.0 off end # PCI bridge
|
||||
device pci 1f.0 on
|
||||
chip superio/ite/it8772f
|
||||
# Skip keyboard init
|
||||
register "skip_keyboard" = "1"
|
||||
# Enable PECI on TMPIN3
|
||||
register "peci_tmpin" = "3"
|
||||
# Enable FAN2
|
||||
register "fan2_enable" = "1"
|
||||
|
||||
device pnp 2e.0 off end # FDC
|
||||
device pnp 2e.1 on # Serial Port 1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.4 on # Environment Controller
|
||||
io 0x60 = 0x700
|
||||
io 0x62 = 0x710
|
||||
irq 0x70 = 0x09
|
||||
irq 0xf2 = 0x20
|
||||
irq 0xf4 = 0x0
|
||||
irq 0xfa = 0x12
|
||||
end
|
||||
device pnp 2e.7 on # GPIO
|
||||
io 0x60 = 0x720
|
||||
io 0x62 = 0x730
|
||||
end
|
||||
device pnp 2e.5 off
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
end # Keyboard
|
||||
device pnp 2e.6 off
|
||||
irq 0x70 = 12
|
||||
end # Mouse
|
||||
device pnp 2e.a off end # IR
|
||||
end
|
||||
end # LPC bridge
|
||||
device pci 1f.2 on end # SATA Controller
|
||||
device pci 1f.3 on end # SMBus
|
||||
device pci 1f.6 on end # Thermal
|
||||
end
|
||||
end
|
||||
|
|
@ -1,56 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2015 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
DefinitionBlock(
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
0x02, // DSDT revision: ACPI v2.0
|
||||
"COREv4", // OEM id
|
||||
"COREBOOT", // OEM table id
|
||||
0x20110725 // OEM revision
|
||||
)
|
||||
{
|
||||
// Some generic macros
|
||||
#include "acpi/platform.asl"
|
||||
|
||||
// global NVS and variables
|
||||
#include <soc/intel/broadwell/acpi/globalnvs.asl>
|
||||
|
||||
// General Purpose Events
|
||||
//#include "acpi/gpe.asl"
|
||||
|
||||
// CPU
|
||||
#include <soc/intel/broadwell/acpi/cpu.asl>
|
||||
|
||||
Scope (\_SB) {
|
||||
Device (PCI0)
|
||||
{
|
||||
#include <soc/intel/broadwell/acpi/systemagent.asl>
|
||||
#include <soc/intel/broadwell/acpi/pch.asl>
|
||||
}
|
||||
}
|
||||
|
||||
// Thermal handler
|
||||
#include "acpi/thermal.asl"
|
||||
|
||||
// Chrome OS specific
|
||||
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
|
||||
|
||||
// Chipset specific sleep states
|
||||
#include <soc/intel/broadwell/acpi/sleepstates.asl>
|
||||
|
||||
// Mainboard specific
|
||||
#include "acpi/mainboard.asl"
|
||||
}
|
||||
|
|
@ -1,154 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2015 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include <device/pci.h>
|
||||
#include <soc/acpi.h>
|
||||
#include <cpu/x86/smm.h>
|
||||
#include <soc/pch.h>
|
||||
#include <soc/iomap.h>
|
||||
|
||||
void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
|
||||
{
|
||||
acpi_header_t *header = &(fadt->header);
|
||||
u16 pmbase = ACPI_BASE_ADDRESS;
|
||||
|
||||
memset((void *) fadt, 0, sizeof(acpi_fadt_t));
|
||||
memcpy(header->signature, "FACP", 4);
|
||||
header->length = sizeof(acpi_fadt_t);
|
||||
header->revision = 5;
|
||||
memcpy(header->oem_id, OEM_ID, 6);
|
||||
memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
|
||||
memcpy(header->asl_compiler_id, ASLC, 4);
|
||||
header->asl_compiler_revision = 1;
|
||||
|
||||
fadt->firmware_ctrl = (unsigned long) facs;
|
||||
fadt->dsdt = (unsigned long) dsdt;
|
||||
fadt->model = 1;
|
||||
fadt->preferred_pm_profile = PM_MOBILE;
|
||||
|
||||
fadt->sci_int = 0x9;
|
||||
fadt->smi_cmd = APM_CNT;
|
||||
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
|
||||
fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
|
||||
fadt->s4bios_req = 0x0;
|
||||
fadt->pstate_cnt = 0;
|
||||
|
||||
fadt->pm1a_evt_blk = pmbase;
|
||||
fadt->pm1b_evt_blk = 0x0;
|
||||
fadt->pm1a_cnt_blk = pmbase + 0x4;
|
||||
fadt->pm1b_cnt_blk = 0x0;
|
||||
fadt->pm2_cnt_blk = pmbase + 0x50;
|
||||
fadt->pm_tmr_blk = pmbase + 0x8;
|
||||
fadt->gpe0_blk = pmbase + 0x80;
|
||||
fadt->gpe1_blk = 0;
|
||||
|
||||
fadt->pm1_evt_len = 4;
|
||||
fadt->pm1_cnt_len = 2;
|
||||
fadt->pm2_cnt_len = 1;
|
||||
fadt->pm_tmr_len = 4;
|
||||
fadt->gpe0_blk_len = 32;
|
||||
fadt->gpe1_blk_len = 0;
|
||||
fadt->gpe1_base = 0;
|
||||
fadt->cst_cnt = 0;
|
||||
fadt->p_lvl2_lat = 1;
|
||||
fadt->p_lvl3_lat = 87;
|
||||
fadt->flush_size = 1024;
|
||||
fadt->flush_stride = 16;
|
||||
fadt->duty_offset = 1;
|
||||
fadt->duty_width = 0;
|
||||
fadt->day_alrm = 0xd;
|
||||
fadt->mon_alrm = 0x00;
|
||||
fadt->century = 0x00;
|
||||
fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
|
||||
|
||||
fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
|
||||
ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
|
||||
ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |
|
||||
ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
|
||||
|
||||
fadt->reset_reg.space_id = 1;
|
||||
fadt->reset_reg.bit_width = 8;
|
||||
fadt->reset_reg.bit_offset = 0;
|
||||
fadt->reset_reg.resv = 0;
|
||||
fadt->reset_reg.addrl = 0xcf9;
|
||||
fadt->reset_reg.addrh = 0;
|
||||
|
||||
fadt->reset_value = 6;
|
||||
fadt->x_firmware_ctl_l = (unsigned long)facs;
|
||||
fadt->x_firmware_ctl_h = 0;
|
||||
fadt->x_dsdt_l = (unsigned long)dsdt;
|
||||
fadt->x_dsdt_h = 0;
|
||||
|
||||
fadt->x_pm1a_evt_blk.space_id = 1;
|
||||
fadt->x_pm1a_evt_blk.bit_width = 32;
|
||||
fadt->x_pm1a_evt_blk.bit_offset = 0;
|
||||
fadt->x_pm1a_evt_blk.resv = 0;
|
||||
fadt->x_pm1a_evt_blk.addrl = pmbase;
|
||||
fadt->x_pm1a_evt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1b_evt_blk.space_id = 1;
|
||||
fadt->x_pm1b_evt_blk.bit_width = 0;
|
||||
fadt->x_pm1b_evt_blk.bit_offset = 0;
|
||||
fadt->x_pm1b_evt_blk.resv = 0;
|
||||
fadt->x_pm1b_evt_blk.addrl = 0x0;
|
||||
fadt->x_pm1b_evt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1a_cnt_blk.space_id = 1;
|
||||
fadt->x_pm1a_cnt_blk.bit_width = 16;
|
||||
fadt->x_pm1a_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm1a_cnt_blk.resv = 0;
|
||||
fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
|
||||
fadt->x_pm1a_cnt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1b_cnt_blk.space_id = 1;
|
||||
fadt->x_pm1b_cnt_blk.bit_width = 0;
|
||||
fadt->x_pm1b_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm1b_cnt_blk.resv = 0;
|
||||
fadt->x_pm1b_cnt_blk.addrl = 0x0;
|
||||
fadt->x_pm1b_cnt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm2_cnt_blk.space_id = 1;
|
||||
fadt->x_pm2_cnt_blk.bit_width = 8;
|
||||
fadt->x_pm2_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm2_cnt_blk.resv = 0;
|
||||
fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
|
||||
fadt->x_pm2_cnt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm_tmr_blk.space_id = 1;
|
||||
fadt->x_pm_tmr_blk.bit_width = 32;
|
||||
fadt->x_pm_tmr_blk.bit_offset = 0;
|
||||
fadt->x_pm_tmr_blk.resv = 0;
|
||||
fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
|
||||
fadt->x_pm_tmr_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_gpe0_blk.space_id = 0;
|
||||
fadt->x_gpe0_blk.bit_width = 0;
|
||||
fadt->x_gpe0_blk.bit_offset = 0;
|
||||
fadt->x_gpe0_blk.resv = 0;
|
||||
fadt->x_gpe0_blk.addrl = 0;
|
||||
fadt->x_gpe0_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_gpe1_blk.space_id = 1;
|
||||
fadt->x_gpe1_blk.bit_width = 0;
|
||||
fadt->x_gpe1_blk.bit_offset = 0;
|
||||
fadt->x_gpe1_blk.resv = 0;
|
||||
fadt->x_gpe1_blk.addrl = 0x0;
|
||||
fadt->x_gpe1_blk.addrh = 0x0;
|
||||
|
||||
header->checksum =
|
||||
acpi_checksum((void *) fadt, header->length);
|
||||
}
|
||||
|
|
@ -1,109 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2013 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* coreboot specific header */
|
||||
0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283
|
||||
0x10ec0283, // Subsystem ID
|
||||
0x0000000c, // Number of jacks (NID entries)
|
||||
|
||||
/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10ec0283 */
|
||||
0x00172083,
|
||||
0x00172102,
|
||||
0x001722ec,
|
||||
0x00172310,
|
||||
|
||||
/* Pin Widget Verb Table */
|
||||
|
||||
/* Pin Complex (NID 0x12) DMIC */
|
||||
0x01271cf0,
|
||||
0x01271d11,
|
||||
0x01271e11,
|
||||
0x01271f41,
|
||||
|
||||
/* Pin Complex (NID 0x14) SPKR-OUT PORTD */
|
||||
0x01471cf0,
|
||||
0x01471d11,
|
||||
0x01471e11,
|
||||
0x01471f40,
|
||||
|
||||
/* Pin Complex (NID 0x17) */
|
||||
0x01771cf0,
|
||||
0x01771d11,
|
||||
0x01771e11,
|
||||
0x01771f41,
|
||||
|
||||
/* Pin Complex (NID 0x18) MIC1 PORTB */
|
||||
0x01971c11, // group 1, cap 1
|
||||
0x01971d10, // black, jack detect
|
||||
0x01971ea7, // mic in, analog
|
||||
0x01971f03, // connector, left panel
|
||||
|
||||
/* Pin Complex (NID 0x19) MIC2 PORTF */
|
||||
0x01871cf0,
|
||||
0x01871d11,
|
||||
0x01871e11,
|
||||
0x01871f41,
|
||||
|
||||
/* Pin Complex (NID 0x1A) LINE1 PORTC */
|
||||
0x01a71cf0,
|
||||
0x01a71d11,
|
||||
0x01a71e11,
|
||||
0x01a71f41,
|
||||
|
||||
/* Pin Complex (NID 0x1B) LINE2 PORTE */
|
||||
0x01a71cf0,
|
||||
0x01a71d11,
|
||||
0x01a71e11,
|
||||
0x01a71f41,
|
||||
|
||||
/* Pin Complex (NID 0x1d) PCBeep */
|
||||
0x01d71c2d, // eapd low on ex-amp, laptop, custom enable
|
||||
0x01d71d81, // mute spkr on hpout
|
||||
0x01d71e15, // pcbeep en able, checksum
|
||||
0x01d71f40, // no physical, internal
|
||||
|
||||
/* Pin Complex (NID 0x1E) SPDIF-OUT */
|
||||
0x01e71cf0,
|
||||
0x01e71d11,
|
||||
0x01e71e11,
|
||||
0x01e71f41,
|
||||
|
||||
/* Pin Complex (NID 0x21) HPOUT PORT-I */
|
||||
0x02171c1f, // group1,
|
||||
0x02171d10, // black, jack detect
|
||||
0x02171e21, // HPOut, 1/8 stereo
|
||||
0x02171f03, // connector, left panel
|
||||
|
||||
/* Undocumented settings from Realtek (needed for beep_gen) */
|
||||
/* Widget node 0x20 */
|
||||
0x02050010,
|
||||
0x02040c20,
|
||||
0x0205001b,
|
||||
0x0204081b,
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {
|
||||
0x00170500, /* power up everything (codec, dac, adc, mixers) */
|
||||
0x01470740, /* enable speaker out */
|
||||
0x01470c02, /* set speaker EAPD pin */
|
||||
0x0143b01f, /* unmute speaker */
|
||||
0x00c37100, /* unmute mixer nid 0xc input 1 */
|
||||
0x00b37410, /* unmute mixer nid 0xb beep input and set volume */
|
||||
};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
|
@ -1,192 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <cbfs.h>
|
||||
#include <string.h>
|
||||
#include <types.h>
|
||||
#include <arch/io.h>
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <fmap.h>
|
||||
#include <southbridge/intel/bd82x6x/pch.h>
|
||||
#include "onboard.h"
|
||||
|
||||
static unsigned int search(char *p, u8 *a, unsigned int lengthp,
|
||||
unsigned int lengtha)
|
||||
{
|
||||
int i, j;
|
||||
|
||||
/* Searching */
|
||||
for (j = 0; j <= lengtha - lengthp; j++) {
|
||||
for (i = 0; i < lengthp && p[i] == a[i + j]; i++)
|
||||
;
|
||||
if (i >= lengthp)
|
||||
return j;
|
||||
}
|
||||
return lengtha;
|
||||
}
|
||||
|
||||
static unsigned char get_hex_digit(u8 *offset)
|
||||
{
|
||||
unsigned char retval = 0;
|
||||
|
||||
retval = *offset - '0';
|
||||
if (retval > 0x09) {
|
||||
retval = *offset - 'A' + 0x0A;
|
||||
if (retval > 0x0F)
|
||||
retval = *offset - 'a' + 0x0a;
|
||||
}
|
||||
if (retval > 0x0F) {
|
||||
printk(BIOS_DEBUG, "Error: Invalid Hex digit found: %c - 0x%02x\n",
|
||||
*offset, *offset);
|
||||
retval = 0;
|
||||
}
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
static int get_mac_address(u32 *high_dword, u32 *low_dword,
|
||||
u8 *search_address, u32 search_length)
|
||||
{
|
||||
char key[] = "ethernet_mac";
|
||||
unsigned int offset;
|
||||
int i;
|
||||
|
||||
offset = search(key, search_address, sizeof(key) - 1, search_length);
|
||||
if (offset == search_length) {
|
||||
printk(BIOS_DEBUG,
|
||||
"Error: Could not locate '%s' in VPD\n", key);
|
||||
return 0;
|
||||
}
|
||||
printk(BIOS_DEBUG, "Located '%s' in VPD\n", key);
|
||||
|
||||
offset += sizeof(key); /* move to next character */
|
||||
*high_dword = 0;
|
||||
|
||||
/* Fetch the MAC address and put the octets in the correct order to
|
||||
* be programmed.
|
||||
*
|
||||
* From RTL8105E_Series_EEPROM-Less_App_Note_1.1
|
||||
* If the MAC address is 001122334455h:
|
||||
* Write 33221100h to I/O register offset 0x00 via double word access
|
||||
* Write 00005544h to I/O register offset 0x04 via double word access
|
||||
*/
|
||||
|
||||
for (i = 0; i < 4; i++) {
|
||||
*high_dword |= (get_hex_digit(search_address + offset)
|
||||
<< (4 + (i * 8)));
|
||||
*high_dword |= (get_hex_digit(search_address + offset + 1)
|
||||
<< (i * 8));
|
||||
offset += 3;
|
||||
}
|
||||
|
||||
*low_dword = 0;
|
||||
for (i = 0; i < 2; i++) {
|
||||
*low_dword |= (get_hex_digit(search_address + offset)
|
||||
<< (4 + (i * 8)));
|
||||
*low_dword |= (get_hex_digit(search_address + offset + 1)
|
||||
<< (i * 8));
|
||||
offset += 3;
|
||||
}
|
||||
|
||||
return *high_dword | *low_dword;
|
||||
}
|
||||
|
||||
static void program_mac_address(u16 io_base)
|
||||
{
|
||||
void *search_address = NULL;
|
||||
size_t search_length = -1;
|
||||
|
||||
/* Default MAC Address of A0:00:BA:D0:0B:AD */
|
||||
u32 high_dword = 0xD0BA00A0; /* high dword of mac address */
|
||||
u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */
|
||||
|
||||
if (IS_ENABLED(CONFIG_CHROMEOS)) {
|
||||
struct region_device rdev;
|
||||
|
||||
if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) {
|
||||
search_address = rdev_mmap_full(&rdev);
|
||||
|
||||
if (search_address != NULL)
|
||||
search_length = region_device_sz(&rdev);
|
||||
}
|
||||
} else {
|
||||
search_address = cbfs_boot_map_with_leak("vpd.bin",
|
||||
CBFS_TYPE_RAW,
|
||||
&search_length);
|
||||
}
|
||||
|
||||
if (search_address == NULL)
|
||||
printk(BIOS_ERR, "LAN: VPD not found.\n");
|
||||
else
|
||||
get_mac_address(&high_dword, &low_dword, search_address,
|
||||
search_length);
|
||||
|
||||
if (io_base) {
|
||||
printk(BIOS_DEBUG, "Realtek NIC io_base = 0x%04x\n", io_base);
|
||||
printk(BIOS_DEBUG, "Programming MAC Address\n");
|
||||
|
||||
/* Disable register protection */
|
||||
outb(0xc0, io_base + 0x50);
|
||||
outl(high_dword, io_base);
|
||||
outl(low_dword, io_base + 0x04);
|
||||
outb(0x60, io_base + 54);
|
||||
/* Enable register protection again */
|
||||
outb(0x00, io_base + 0x50);
|
||||
}
|
||||
}
|
||||
|
||||
void lan_init(void)
|
||||
{
|
||||
u16 io_base = 0;
|
||||
struct device *ethernet_dev = NULL;
|
||||
|
||||
/* Get NIC's IO base address */
|
||||
ethernet_dev = dev_find_device(RIKKU_NIC_VENDOR_ID,
|
||||
RIKKU_NIC_DEVICE_ID, 0);
|
||||
if (ethernet_dev != NULL) {
|
||||
io_base = pci_read_config16(ethernet_dev, 0x10) & 0xfffe;
|
||||
|
||||
/*
|
||||
* Battery life time - LAN PCIe should enter ASPM L1 to save
|
||||
* power when LAN connection is idle.
|
||||
* enable CLKREQ: LAN pci config space 0x81h=01
|
||||
*/
|
||||
pci_write_config8(ethernet_dev, 0x81, 0x01);
|
||||
}
|
||||
|
||||
if (io_base) {
|
||||
/* Program MAC address based on VPD data */
|
||||
program_mac_address(io_base);
|
||||
|
||||
/*
|
||||
* Program NIC LEDS
|
||||
*
|
||||
* RTL8105E Series EEPROM-Less Application Note,
|
||||
* Section 5.6 LED Mode Configuration
|
||||
*
|
||||
* Step1: Write C0h to I/O register 0x50 via byte access to
|
||||
* disable 'register protection'
|
||||
* Step2: Write xx001111b to I/O register 0x52 via byte access
|
||||
* (bit7 is LEDS1 and bit6 is LEDS0)
|
||||
* Step3: Write 0x00 to I/O register 0x50 via byte access to
|
||||
* enable 'register protection'
|
||||
*/
|
||||
outb(0xc0, io_base + 0x50); /* Disable protection */
|
||||
outb((RIKKU_NIC_LED_MODE << 6) | 0x0f, io_base + 0x52);
|
||||
outb(0x00, io_base + 0x50); /* Enable register protection */
|
||||
}
|
||||
}
|
||||
|
|
@ -1,44 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2015 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/io.h>
|
||||
#include <vendorcode/google/chromeos/chromeos.h>
|
||||
#include "onboard.h"
|
||||
|
||||
void mainboard_suspend_resume(void)
|
||||
{
|
||||
/* Call SMM finalize() handlers before resume */
|
||||
outb(0xcb, 0xb2);
|
||||
}
|
||||
|
||||
static void mainboard_init(device_t dev)
|
||||
{
|
||||
lan_init();
|
||||
}
|
||||
|
||||
// mainboard_enable is executed as first thing after
|
||||
// enumerate_buses().
|
||||
|
||||
static void mainboard_enable(device_t dev)
|
||||
{
|
||||
dev->ops->init = mainboard_init;
|
||||
dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
|
|
@ -1,42 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef ONBOARD_H
|
||||
#define ONBOARD_H
|
||||
|
||||
#ifndef __ACPI__
|
||||
void lan_init(void);
|
||||
#endif
|
||||
|
||||
/* defines for programming the MAC address */
|
||||
#define RIKKU_NIC_VENDOR_ID 0x10EC
|
||||
#define RIKKU_NIC_DEVICE_ID 0x8168
|
||||
|
||||
/* 0x00: White LINK LED and Amber ACTIVE LED */
|
||||
#define RIKKU_NIC_LED_MODE 0x00
|
||||
|
||||
/* NIC wake is GPIO 8 */
|
||||
#define RIKKU_NIC_WAKE_GPIO 8
|
||||
|
||||
/* WLAN wake is GPIO 10 */
|
||||
#define RIKKU_WLAN_WAKE_GPIO 10
|
||||
|
||||
/* IT8772F defs */
|
||||
#define IT8772F_BASE 0x2e
|
||||
#define IT8772F_SERIAL_DEV PNP_DEV(IT8772F_BASE, IT8772F_SP1)
|
||||
#define IT8772F_GPIO_DEV PNP_DEV(IT8772F_BASE, IT8772F_GPIO)
|
||||
#define IT8772F_DUMMY_DEV PNP_DEV(IT8772F_BASE, 0)
|
||||
|
||||
#endif
|
||||
|
|
@ -1,63 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2010 coresystems GmbH
|
||||
* Copyright (C) 2015 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <cbfs.h>
|
||||
#include <console/console.h>
|
||||
#include <string.h>
|
||||
#include <ec/google/chromeec/ec.h>
|
||||
#include <soc/gpio.h>
|
||||
#include <soc/pei_data.h>
|
||||
#include <soc/pei_wrapper.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <mainboard/google/rikku/spd/spd.h>
|
||||
#include <superio/ite/common/ite.h>
|
||||
#include <superio/ite/it8772f/it8772f.h>
|
||||
#include "gpio.h"
|
||||
#include "onboard.h"
|
||||
|
||||
void mainboard_romstage_entry(struct romstage_params *rp)
|
||||
{
|
||||
struct pei_data pei_data;
|
||||
|
||||
post_code(0x32);
|
||||
|
||||
/* Initialize GPIOs */
|
||||
init_gpios(mainboard_gpio_config);
|
||||
|
||||
/* Fill out PEI DATA */
|
||||
memset(&pei_data, 0, sizeof(pei_data));
|
||||
mainboard_fill_pei_data(&pei_data);
|
||||
mainboard_fill_spd_data(&pei_data);
|
||||
rp->pei_data = &pei_data;
|
||||
|
||||
/* Call into the real romstage main with this board's attributes. */
|
||||
romstage_common(rp);
|
||||
}
|
||||
|
||||
void mainboard_pre_console_init(void)
|
||||
{
|
||||
/* Early SuperIO setup */
|
||||
ite_kill_watchdog(IT8772F_GPIO_DEV);
|
||||
it8772f_ac_resume_southbridge(IT8772F_DUMMY_DEV);
|
||||
ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
|
||||
/* Turn On GPIO10.LED */
|
||||
it8772f_gpio_led(IT8772F_GPIO_DEV, 1 /* set */, 0x01 /* select */,
|
||||
0x00 /* polarity: non-inverting */, 0x00 /* 0=pulldown */,
|
||||
0x01 /* output */, 0x01 /* 1=Simple IO function */,
|
||||
SIO_GPIO_BLINK_GPIO10, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ);
|
||||
|
||||
}
|
||||
|
|
@ -1,89 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008-2009 coresystems GmbH
|
||||
* Copyright 2014 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/io.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/x86/smm.h>
|
||||
#include <soc/pm.h>
|
||||
#include <soc/smm.h>
|
||||
#include <elog.h>
|
||||
#include <ec/google/chromeec/ec.h>
|
||||
#include <soc/gpio.h>
|
||||
#include <soc/iomap.h>
|
||||
#include <soc/nvs.h>
|
||||
#include <soc/pm.h>
|
||||
#include <soc/smm.h>
|
||||
#include <superio/ite/it8772f/it8772f.h>
|
||||
#include "onboard.h"
|
||||
|
||||
int mainboard_io_trap_handler(int smif)
|
||||
{
|
||||
switch (smif) {
|
||||
case 0x99:
|
||||
printk(BIOS_DEBUG, "Sample\n");
|
||||
smm_get_gnvs()->smif = 0;
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* On success, the IO Trap Handler returns 0
|
||||
* On failure, the IO Trap Handler returns a value != 0
|
||||
*
|
||||
* For now, we force the return value to 0 and log all traps to
|
||||
* see what's going on.
|
||||
*/
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* gpi_sts is GPIO 47:32 */
|
||||
void mainboard_smi_gpi(u32 gpi_sts)
|
||||
{
|
||||
}
|
||||
|
||||
void mainboard_smi_sleep(u8 slp_typ)
|
||||
{
|
||||
/* Disable USB charging if required */
|
||||
switch (slp_typ) {
|
||||
case ACPI_S3:
|
||||
it8772f_gpio_led(IT8772F_GPIO_DEV, 1 /* set */, 0x01 /* select */,
|
||||
0x01 /* polarity */, 0x01 /* 1=pullup */,
|
||||
0x01 /* output */, 0x00, /* 0=Alternate function */
|
||||
SIO_GPIO_BLINK_GPIO10, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ);
|
||||
break;
|
||||
case ACPI_S5:
|
||||
it8772f_gpio_led(IT8772F_GPIO_DEV, 1 /* set */, 0x01 /* select */,
|
||||
0x00 /* polarity: non-inverting */, 0x00 /* 0=pulldown */,
|
||||
0x01 /* output */, 0x01 /* 1=Simple IO function */,
|
||||
SIO_GPIO_BLINK_GPIO10, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
int mainboard_smi_apmc(u8 apmc)
|
||||
{
|
||||
switch (apmc) {
|
||||
case APM_CNT_ACPI_ENABLE:
|
||||
break;
|
||||
case APM_CNT_ACPI_DISABLE:
|
||||
break;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1,16 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2015 Google Inc.
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
|
||||
romstage-y += spd.c
|
||||
|
|
@ -1,31 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <soc/pei_data.h>
|
||||
#include <mainboard/google/rikku/spd/spd.h>
|
||||
|
||||
/* Copy SPD data for on-board memory */
|
||||
void mainboard_fill_spd_data(struct pei_data *pei_data)
|
||||
{
|
||||
pei_data->spd_addresses[0] = 0xa0;
|
||||
pei_data->spd_addresses[1] = 0x00;
|
||||
pei_data->spd_addresses[2] = 0xa4;
|
||||
pei_data->spd_addresses[3] = 0x00;
|
||||
pei_data->dimm_channel0_disabled = 2;
|
||||
pei_data->dimm_channel1_disabled = 2;
|
||||
// Enable 2x refresh mode
|
||||
pei_data->ddr_refresh_2x = 1;
|
||||
pei_data->dq_pins_interleaved = 1;
|
||||
}
|
||||
|
|
@ -1,22 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef MAINBOARD_SPD_H
|
||||
#define MAINBOARD_SPD_H
|
||||
|
||||
struct pei_data;
|
||||
void mainboard_fill_spd_data(struct pei_data *pei_data);
|
||||
|
||||
#endif
|
||||
|
|
@ -1,59 +0,0 @@
|
|||
if BOARD_GOOGLE_TIDUS
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
def_bool y
|
||||
select SOC_INTEL_BROADWELL
|
||||
select BOARD_ROMSIZE_KB_8192
|
||||
select SUPERIO_ITE_IT8772F
|
||||
select HAVE_ACPI_TABLES
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_ACPI_RESUME
|
||||
select HAVE_SMI_HANDLER
|
||||
select MAINBOARD_HAS_CHROMEOS
|
||||
select MAINBOARD_HAS_LPC_TPM
|
||||
|
||||
config CHROMEOS
|
||||
select CHROMEOS_RAMOOPS_DYNAMIC
|
||||
select PHYSICAL_REC_SWITCH
|
||||
select VBOOT_VBNV_CMOS
|
||||
select VIRTUAL_DEV_SWITCH
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default google/tidus
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "Tidus"
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 18
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 8
|
||||
|
||||
config VGA_BIOS_FILE
|
||||
string
|
||||
default "pci8086,0166.rom"
|
||||
|
||||
config HAVE_IFD_BIN
|
||||
bool
|
||||
default n
|
||||
|
||||
config HAVE_ME_BIN
|
||||
bool
|
||||
default n
|
||||
|
||||
|
||||
config MAINBOARD_FAMILY
|
||||
string
|
||||
depends on GENERATE_SMBIOS_TABLES
|
||||
default "Google_Tidus"
|
||||
|
||||
config GBB_HWID
|
||||
string
|
||||
depends on CHROMEOS
|
||||
default "TIDUS TEST A-A 0595"
|
||||
endif
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
config BOARD_GOOGLE_TIDUS
|
||||
bool "Tidus"
|
||||
|
|
@ -1,24 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2014 Google Inc.
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
|
||||
subdirs-y += spd
|
||||
romstage-$(CONFIG_CHROMEOS) += chromeos.c
|
||||
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
|
||||
ramstage-y += lan.c
|
||||
|
||||
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c led.c
|
||||
|
||||
romstage-y += pei_data.c led.c
|
||||
ramstage-y += pei_data.c
|
||||
|
|
@ -1,82 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* This is board specific information: IRQ routing for IvyBridge */
|
||||
|
||||
// PCI Interrupt Routing
|
||||
Method(_PRT)
|
||||
{
|
||||
If (PICM) {
|
||||
Return (Package() {
|
||||
// Onboard graphics (IGD) 0:2.0
|
||||
Package() { 0x0002ffff, 0, 0, 16 },
|
||||
// Mini-HD Audio 0:3.0
|
||||
Package() { 0x0003ffff, 0, 0, 16 },
|
||||
// High Definition Audio 0:1b.0
|
||||
Package() { 0x001bffff, 0, 0, 22 },
|
||||
// PCIe Root Ports 0:1c.x
|
||||
Package() { 0x001cffff, 0, 0, 16 },
|
||||
Package() { 0x001cffff, 1, 0, 17 },
|
||||
Package() { 0x001cffff, 2, 0, 18 },
|
||||
Package() { 0x001cffff, 3, 0, 19 },
|
||||
// EHCI 0:1d.0
|
||||
Package() { 0x001dffff, 0, 0, 19 },
|
||||
// XHCI 0:14.0
|
||||
Package() { 0x0014ffff, 0, 0, 18 },
|
||||
// LPC devices 0:1f.0
|
||||
Package() { 0x001fffff, 0, 0, 22 },
|
||||
Package() { 0x001fffff, 1, 0, 18 },
|
||||
Package() { 0x001fffff, 2, 0, 17 },
|
||||
Package() { 0x001fffff, 3, 0, 16 },
|
||||
// Serial IO 0:15.0
|
||||
Package() { 0x0015ffff, 0, 0, 20 },
|
||||
Package() { 0x0015ffff, 1, 0, 21 },
|
||||
Package() { 0x0015ffff, 2, 0, 21 },
|
||||
Package() { 0x0015ffff, 3, 0, 21 },
|
||||
// SDIO 0:17.0
|
||||
Package() { 0x0017ffff, 0, 0, 23 },
|
||||
})
|
||||
} Else {
|
||||
Return (Package() {
|
||||
// Onboard graphics (IGD) 0:2.0
|
||||
Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
|
||||
// Mini-HD Audio 0:3.0
|
||||
Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
|
||||
// High Definition Audio 0:1b.0
|
||||
Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
|
||||
// PCIe Root Ports 0:1c.x
|
||||
Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
|
||||
Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
|
||||
Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
|
||||
Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
|
||||
// EHCI 0:1d.0
|
||||
Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
|
||||
// XHCI 0:14.0
|
||||
Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
|
||||
// LPC device 0:1f.0
|
||||
Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
|
||||
Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
|
||||
Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
|
||||
Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
|
||||
// Serial IO 0:15.0
|
||||
Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
|
||||
Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
|
||||
Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 },
|
||||
Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 },
|
||||
// SDIO 0:17.0
|
||||
Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
|
||||
})
|
||||
}
|
||||
}
|
||||
|
|
@ -1,69 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <mainboard/google/tidus/onboard.h>
|
||||
|
||||
Scope (\_SB)
|
||||
{
|
||||
Device (PWRB)
|
||||
{
|
||||
Name(_HID, EisaId("PNP0C0C"))
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* LAN connected to Root Port 3, becomes Root Port 1 after coalesce
|
||||
*/
|
||||
Scope (\_SB.PCI0.RP01)
|
||||
{
|
||||
Device (ETH0)
|
||||
{
|
||||
Name (_ADR, 0x00000000)
|
||||
Name (_PRW, Package() { TIDUS_NIC_WAKE_GPIO, 3 })
|
||||
|
||||
Method (_DSW, 3, NotSerialized)
|
||||
{
|
||||
Store (TIDUS_NIC_WAKE_GPIO, Local0)
|
||||
|
||||
If (LEqual (Arg0, 1)) {
|
||||
// Enable GPIO as wake source
|
||||
\_SB.PCI0.LPCB.GPIO.GWAK (Local0)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* WLAN connected to Root Port 4, becomes Root Port 2 after coalesce
|
||||
*/
|
||||
Scope (\_SB.PCI0.RP02)
|
||||
{
|
||||
Device (WLAN)
|
||||
{
|
||||
Name (_ADR, 0x00000000)
|
||||
Name (_PRW, Package() { TIDUS_WLAN_WAKE_GPIO, 3 })
|
||||
|
||||
Method (_DSW, 3, NotSerialized)
|
||||
{
|
||||
Store (TIDUS_WLAN_WAKE_GPIO, Local0)
|
||||
|
||||
If (LEqual (Arg0, 1)) {
|
||||
// Enable GPIO as wake source
|
||||
\_SB.PCI0.LPCB.GPIO.GWAK (Local0)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,71 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* The APM port can be used for generating software SMIs */
|
||||
|
||||
OperationRegion (APMP, SystemIO, 0xb2, 2)
|
||||
Field (APMP, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
APMC, 8, // APM command
|
||||
APMS, 8 // APM status
|
||||
}
|
||||
|
||||
/* Port 80 POST */
|
||||
|
||||
OperationRegion (POST, SystemIO, 0x80, 1)
|
||||
Field (POST, ByteAcc, Lock, Preserve)
|
||||
{
|
||||
DBG0, 8
|
||||
}
|
||||
|
||||
/* SMI I/O Trap */
|
||||
Method(TRAP, 1, Serialized)
|
||||
{
|
||||
Store (Arg0, SMIF) // SMI Function
|
||||
Store (0, TRP0) // Generate trap
|
||||
Return (SMIF) // Return value of SMI handler
|
||||
}
|
||||
|
||||
/* The _PIC method is called by the OS to choose between interrupt
|
||||
* routing via the i8259 interrupt controller or the APIC.
|
||||
*
|
||||
* _PIC is called with a parameter of 0 for i8259 configuration and
|
||||
* with a parameter of 1 for Local Apic/IOAPIC configuration.
|
||||
*/
|
||||
|
||||
Method(_PIC, 1)
|
||||
{
|
||||
// Remember the OS' IRQ routing choice.
|
||||
Store(Arg0, PICM)
|
||||
}
|
||||
|
||||
/* The _PTS method (Prepare To Sleep) is called before the OS is
|
||||
* entering a sleep state. The sleep state number is passed in Arg0
|
||||
*/
|
||||
|
||||
Method(_PTS,1)
|
||||
{
|
||||
}
|
||||
|
||||
/* The _WAK method is called on system wakeup */
|
||||
|
||||
Method(_WAK,1)
|
||||
{
|
||||
/* Initialize thermal defaults */
|
||||
\_TZ.THRM._INI ()
|
||||
|
||||
Return(Package(){0,0})
|
||||
}
|
||||
|
|
@ -1,31 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* Values should match those defined in devicetree.cb */
|
||||
|
||||
#undef SIO_ENABLE_FDC0 // pnp 2e.0: Disable Floppy Controller
|
||||
#undef SIO_ENABLE_INFR // pnp 2e.a: Disable Consumer IR
|
||||
|
||||
#undef SIO_ENABLE_PS2K // pnp 2e.5: Disable PS/2 Keyboard
|
||||
#undef SIO_ENABLE_PS2M // pnp 2e.6: Disable PS/2 Mouse
|
||||
#define SIO_ENABLE_COM1 // pnp 2e.1: Enable Serial Port 1
|
||||
#define SIO_ENABLE_ENVC // pnp 2e.4: Enable Environmental Controller
|
||||
#define SIO_ENVC_IO0 0x700 // pnp 2e.4: io 0x60
|
||||
#define SIO_ENVC_IO1 0x710 // pnp 2e.4: io 0x62
|
||||
#define SIO_ENABLE_GPIO // pnp 2e.7: Enable GPIO
|
||||
#define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60
|
||||
#define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60
|
||||
|
||||
#include "superio/ite/it8772f/acpi/superio.asl"
|
||||
|
|
@ -1,38 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
// Brightness write
|
||||
Method (BRTW, 1, Serialized)
|
||||
{
|
||||
// TODO
|
||||
}
|
||||
|
||||
// Hot Key Display Switch
|
||||
Method (HKDS, 1, Serialized)
|
||||
{
|
||||
// TODO
|
||||
}
|
||||
|
||||
// Lid Switch Display Switch
|
||||
Method (LSDS, 1, Serialized)
|
||||
{
|
||||
// TODO
|
||||
}
|
||||
|
||||
// Brightness Notification
|
||||
Method(BRTN,1,Serialized)
|
||||
{
|
||||
// TODO (no displays defined yet)
|
||||
}
|
||||
|
|
@ -1,63 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <types.h>
|
||||
#include <string.h>
|
||||
#include <cbmem.h>
|
||||
#include <console/console.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <arch/acpigen.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <soc/acpi.h>
|
||||
#include <soc/nvs.h>
|
||||
#include "thermal.h"
|
||||
|
||||
|
||||
static void acpi_update_thermal_table(global_nvs_t *gnvs)
|
||||
{
|
||||
gnvs->tcrt = CRITICAL_TEMPERATURE;
|
||||
gnvs->tpsv = PASSIVE_TEMPERATURE;
|
||||
gnvs->tmax = MAX_TEMPERATURE;
|
||||
gnvs->flvl = 1;
|
||||
}
|
||||
|
||||
void acpi_create_gnvs(global_nvs_t *gnvs)
|
||||
{
|
||||
acpi_init_gnvs(gnvs);
|
||||
|
||||
/* Enable USB ports in S3 */
|
||||
gnvs->s3u0 = 1;
|
||||
|
||||
/* Disable USB ports in S5 */
|
||||
gnvs->s5u0 = 0;
|
||||
|
||||
acpi_update_thermal_table(gnvs);
|
||||
}
|
||||
|
||||
unsigned long acpi_fill_madt(unsigned long current)
|
||||
{
|
||||
/* Local APICs */
|
||||
current = acpi_create_madt_lapics(current);
|
||||
|
||||
/* IOAPIC */
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
|
||||
2, IO_APIC_ADDR, 0);
|
||||
|
||||
return acpi_madt_irq_overrides(current);
|
||||
}
|
||||
|
|
@ -1,7 +0,0 @@
|
|||
Vendor name: Lenovo
|
||||
Board name: ThinkCentre Chromebox
|
||||
Category: half
|
||||
ROM package: SOIC-8
|
||||
ROM protocol: SPI
|
||||
ROM socketed: n
|
||||
Flashrom support: y
|
||||
|
|
@ -1,105 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <console/console.h>
|
||||
#include <vendorcode/google/chromeos/chromeos.h>
|
||||
#include <ec/google/chromeec/ec.h>
|
||||
#include <soc/gpio.h>
|
||||
#include <soc/sata.h>
|
||||
|
||||
#define GPIO_SPI_WP 58
|
||||
#define GPIO_REC_MODE 12
|
||||
|
||||
#define FLAG_SPI_WP 0
|
||||
#define FLAG_REC_MODE 1
|
||||
#define FLAG_DEV_MODE 2
|
||||
|
||||
#ifndef __PRE_RAM__
|
||||
#include <boot/coreboot_tables.h>
|
||||
|
||||
void fill_lb_gpios(struct lb_gpios *gpios)
|
||||
{
|
||||
struct lb_gpio chromeos_gpios[] = {
|
||||
{GPIO_SPI_WP, ACTIVE_HIGH, 0, "write protect"},
|
||||
{GPIO_REC_MODE, ACTIVE_LOW,
|
||||
get_recovery_mode_switch(), "recovery"},
|
||||
{-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"},
|
||||
{-1, ACTIVE_HIGH, 1, "lid"},
|
||||
{-1, ACTIVE_HIGH, 0, "power"},
|
||||
{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
|
||||
};
|
||||
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
|
||||
}
|
||||
#endif
|
||||
|
||||
int get_write_protect_state(void)
|
||||
{
|
||||
device_t dev;
|
||||
#ifdef __PRE_RAM__
|
||||
dev = PCI_DEV(0, 0x1f, 2);
|
||||
#else
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
|
||||
#endif
|
||||
return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;
|
||||
}
|
||||
|
||||
int get_developer_mode_switch(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int get_recovery_mode_switch(void)
|
||||
{
|
||||
device_t dev;
|
||||
#ifdef __PRE_RAM__
|
||||
dev = PCI_DEV(0, 0x1f, 2);
|
||||
#else
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
|
||||
#endif
|
||||
return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;
|
||||
}
|
||||
|
||||
#ifdef __PRE_RAM__
|
||||
void save_chromeos_gpios(void)
|
||||
{
|
||||
u32 flags = 0;
|
||||
|
||||
/* Write Protect: GPIO58 = GPIO_SPI_WP, active high */
|
||||
if (get_gpio(GPIO_SPI_WP))
|
||||
flags |= (1 << FLAG_SPI_WP);
|
||||
|
||||
/* Recovery: GPIO12 = RECOVERY_L, active low */
|
||||
if (!get_gpio(GPIO_REC_MODE))
|
||||
flags |= (1 << FLAG_REC_MODE);
|
||||
|
||||
/* Developer: Virtual */
|
||||
|
||||
pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags);
|
||||
}
|
||||
#endif
|
||||
|
||||
static const struct cros_gpio cros_gpios[] = {
|
||||
CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME),
|
||||
CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
|
||||
};
|
||||
|
||||
void mainboard_chromeos_acpi_generate(void)
|
||||
{
|
||||
chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
|
||||
}
|
||||
|
|
@ -1,38 +0,0 @@
|
|||
FLASH@0xff800000 0x800000 {
|
||||
SI_ALL@0x0 0x200000 {
|
||||
SI_DESC@0x0 0x1000
|
||||
SI_ME@0x1000 0x1ff000
|
||||
}
|
||||
SI_BIOS@0x200000 0x600000 {
|
||||
RW_SECTION_A@0x0 0xf0000 {
|
||||
VBLOCK_A@0x0 0x10000
|
||||
FW_MAIN_A(CBFS)@0x10000 0xdffc0
|
||||
RW_FWID_A@0xeffc0 0x40
|
||||
}
|
||||
RW_SECTION_B@0xf0000 0xf0000 {
|
||||
VBLOCK_B@0x0 0x10000
|
||||
FW_MAIN_B(CBFS)@0x10000 0xdffc0
|
||||
RW_FWID_B@0xeffc0 0x40
|
||||
}
|
||||
RW_MRC_CACHE@0x1e0000 0x10000
|
||||
RW_ELOG@0x1f0000 0x4000
|
||||
RW_SHARED@0x1f4000 0x4000 {
|
||||
SHARED_DATA@0x0 0x2000
|
||||
VBLOCK_DEV@0x2000 0x2000
|
||||
}
|
||||
RW_VPD@0x1f8000 0x2000
|
||||
RW_UNUSED@0x1fa000 0x6000
|
||||
RW_LEGACY(CBFS)@0x200000 0x200000
|
||||
WP_RO@0x400000 0x200000 {
|
||||
RO_VPD@0x0 0x4000
|
||||
RO_UNUSED@0x4000 0xc000
|
||||
RO_SECTION@0x10000 0x1f0000 {
|
||||
FMAP@0x0 0x800
|
||||
RO_FRID@0x800 0x40
|
||||
RO_FRID_PAD@0x840 0x7c0
|
||||
GBB@0x1000 0xef000
|
||||
COREBOOT(CBFS)@0xf0000 0x100000
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,132 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007-2008 coresystems GmbH
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
entries
|
||||
|
||||
#start-bit length config config-ID name
|
||||
#0 8 r 0 seconds
|
||||
#8 8 r 0 alarm_seconds
|
||||
#16 8 r 0 minutes
|
||||
#24 8 r 0 alarm_minutes
|
||||
#32 8 r 0 hours
|
||||
#40 8 r 0 alarm_hours
|
||||
#48 8 r 0 day_of_week
|
||||
#56 8 r 0 day_of_month
|
||||
#64 8 r 0 month
|
||||
#72 8 r 0 year
|
||||
# -----------------------------------------------------------------
|
||||
# Status Register A
|
||||
#80 4 r 0 rate_select
|
||||
#84 3 r 0 REF_Clock
|
||||
#87 1 r 0 UIP
|
||||
# -----------------------------------------------------------------
|
||||
# Status Register B
|
||||
#88 1 r 0 auto_switch_DST
|
||||
#89 1 r 0 24_hour_mode
|
||||
#90 1 r 0 binary_values_enable
|
||||
#91 1 r 0 square-wave_out_enable
|
||||
#92 1 r 0 update_finished_enable
|
||||
#93 1 r 0 alarm_interrupt_enable
|
||||
#94 1 r 0 periodic_interrupt_enable
|
||||
#95 1 r 0 disable_clock_updates
|
||||
# -----------------------------------------------------------------
|
||||
# Status Register C
|
||||
#96 4 r 0 status_c_rsvd
|
||||
#100 1 r 0 uf_flag
|
||||
#101 1 r 0 af_flag
|
||||
#102 1 r 0 pf_flag
|
||||
#103 1 r 0 irqf_flag
|
||||
# -----------------------------------------------------------------
|
||||
# Status Register D
|
||||
#104 7 r 0 status_d_rsvd
|
||||
#111 1 r 0 valid_cmos_ram
|
||||
# -----------------------------------------------------------------
|
||||
# Diagnostic Status Register
|
||||
#112 8 r 0 diag_rsvd1
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
0 120 r 0 reserved_memory
|
||||
#120 264 r 0 unused
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||
384 1 e 4 boot_option
|
||||
388 4 h 0 reboot_counter
|
||||
#390 2 r 0 unused?
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
# coreboot config options: console
|
||||
392 3 e 5 baud_rate
|
||||
395 4 e 6 debug_level
|
||||
#399 1 r 0 unused
|
||||
|
||||
# coreboot config options: cpu
|
||||
400 1 e 2 hyper_threading
|
||||
#401 7 r 0 unused
|
||||
|
||||
# coreboot config options: southbridge
|
||||
408 1 e 1 nmi
|
||||
409 2 e 7 power_on_after_fail
|
||||
#411 5 r 0 unused
|
||||
|
||||
# coreboot config options: bootloader
|
||||
#Used by ChromeOS:
|
||||
416 128 r 0 vbnv
|
||||
#544 440 r 0 unused
|
||||
|
||||
# SandyBridge MRC Scrambler Seed values
|
||||
896 32 r 0 mrc_scrambler_seed
|
||||
928 32 r 0 mrc_scrambler_seed_s3
|
||||
|
||||
# coreboot config options: check sums
|
||||
984 16 h 0 check_sum
|
||||
#1000 24 r 0 amd_reserved
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
5 0 115200
|
||||
5 1 57600
|
||||
5 2 38400
|
||||
5 3 19200
|
||||
5 4 9600
|
||||
5 5 4800
|
||||
5 6 2400
|
||||
5 7 1200
|
||||
6 1 Emergency
|
||||
6 2 Alert
|
||||
6 3 Critical
|
||||
6 4 Error
|
||||
6 5 Warning
|
||||
6 6 Notice
|
||||
6 7 Info
|
||||
6 8 Debug
|
||||
6 9 Spew
|
||||
7 0 Disable
|
||||
7 1 Enable
|
||||
7 2 Keep
|
||||
# -----------------------------------------------------------------
|
||||
checksums
|
||||
|
||||
checksum 392 415 984
|
||||
|
|
@ -1,125 +0,0 @@
|
|||
chip soc/intel/broadwell
|
||||
|
||||
# Disable eDP Hotplug
|
||||
register "gpu_dp_d_hotplug" = "0x00"
|
||||
|
||||
# Enable DisplayPort C Hotplug with 6ms pulse
|
||||
register "gpu_dp_c_hotplug" = "0x06"
|
||||
|
||||
# Enable HDMI Hotplug with 6ms pulse
|
||||
register "gpu_dp_b_hotplug" = "0x06"
|
||||
|
||||
register "pirqa_routing" = "0x8b"
|
||||
register "pirqb_routing" = "0x8a"
|
||||
register "pirqc_routing" = "0x8b"
|
||||
register "pirqd_routing" = "0x8b"
|
||||
register "pirqe_routing" = "0x80"
|
||||
register "pirqf_routing" = "0x80"
|
||||
register "pirqg_routing" = "0x80"
|
||||
register "pirqh_routing" = "0x80"
|
||||
|
||||
# SuperIO range is 0x700-0x73f
|
||||
register "gen2_dec" = "0x003c0701"
|
||||
|
||||
register "alt_gp_smi_en" = "0x0000"
|
||||
register "gpe0_en_1" = "0x00000000"
|
||||
register "gpe0_en_2" = "0x00000000"
|
||||
register "gpe0_en_3" = "0x00000000"
|
||||
register "gpe0_en_4" = "0x00000000"
|
||||
|
||||
register "sata_port_map" = "0x1"
|
||||
register "sata_devslp_disable" = "0x1"
|
||||
|
||||
register "sio_acpi_mode" = "0"
|
||||
register "sio_i2c0_voltage" = "0" # 3.3V
|
||||
register "sio_i2c1_voltage" = "0" # 3.3V
|
||||
|
||||
# Force enable ASPM for PCIe Port 4
|
||||
register "pcie_port_force_aspm" = "0x10"
|
||||
|
||||
# Enable port coalescing
|
||||
register "pcie_port_coalesce" = "1"
|
||||
|
||||
# Disable PCIe CLKOUT 1,5 and CLKOUT_XDP
|
||||
register "icc_clock_disable" = "0x01220000"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # host bridge
|
||||
device pci 02.0 on end # vga controller
|
||||
device pci 03.0 on end # mini-hd audio
|
||||
device pci 13.0 off end # Smart Sound Audio DSP
|
||||
device pci 14.0 on end # USB3 XHCI
|
||||
device pci 15.0 off end # Serial I/O DMA
|
||||
device pci 15.1 off end # I2C0
|
||||
device pci 15.2 off end # I2C1
|
||||
device pci 15.3 off end # GSPI0
|
||||
device pci 15.4 off end # GSPI1
|
||||
device pci 15.5 off end # UART0
|
||||
device pci 15.6 off end # UART1
|
||||
device pci 16.0 on end # Management Engine Interface 1
|
||||
device pci 16.1 off end # Management Engine Interface 2
|
||||
device pci 16.2 off end # Management Engine IDE-R
|
||||
device pci 16.3 off end # Management Engine KT
|
||||
device pci 17.0 off end # SDIO
|
||||
device pci 19.0 off end # GbE
|
||||
device pci 1b.0 on end # High Definition Audio
|
||||
device pci 1c.0 off end # PCIe Port #1
|
||||
device pci 1c.1 off end # PCIe Port #2
|
||||
device pci 1c.2 on end # PCIe Port #3
|
||||
device pci 1c.3 on end # PCIe Port #4
|
||||
device pci 1c.4 on end # PCIe Port #5
|
||||
device pci 1c.5 off end # PCIe Port #6
|
||||
device pci 1d.0 on end # USB2 EHCI
|
||||
device pci 1e.0 off end # PCI bridge
|
||||
device pci 1f.0 on
|
||||
chip superio/ite/it8772f
|
||||
# Skip keyboard init
|
||||
register "skip_keyboard" = "1"
|
||||
# Enable PECI on TMPIN3
|
||||
register "peci_tmpin" = "3"
|
||||
# Enable Thermal Diode on TMPIN1
|
||||
register "tmpin1_mode" = "0"
|
||||
# Enable Thermal Diode on TMPIN2
|
||||
register "tmpin2_mode" = "1"
|
||||
# Enable FAN2
|
||||
register "fan2_enable" = "1"
|
||||
# Default FAN2 speed
|
||||
register "fan2_speed" = "0x4d"
|
||||
|
||||
device pnp 2e.0 off end # FDC
|
||||
device pnp 2e.1 on # Serial Port 1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.4 on # Environment Controller
|
||||
io 0x60 = 0x700
|
||||
io 0x62 = 0x710
|
||||
irq 0x70 = 0x09
|
||||
irq 0xf2 = 0x20
|
||||
irq 0xf4 = 0x0
|
||||
irq 0xfa = 0x12
|
||||
end
|
||||
device pnp 2e.7 on # GPIO
|
||||
io 0x60 = 0x720
|
||||
io 0x62 = 0x730
|
||||
end
|
||||
device pnp 2e.5 off
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
end # Keyboard
|
||||
device pnp 2e.6 off
|
||||
irq 0x70 = 12
|
||||
end # Mouse
|
||||
device pnp 2e.a off end # IR
|
||||
end
|
||||
end # LPC bridge
|
||||
device pci 1f.2 on end # SATA Controller
|
||||
device pci 1f.3 on end # SMBus
|
||||
device pci 1f.6 on end # Thermal
|
||||
end
|
||||
end
|
||||
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Reference in New Issue