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soc/intel/xeon_sp: Move SMBIOS type 4 override functions from mainboard 

to soc

Move SMBIOS type 4 override functions from mainboard to soc so that all
xeon family cpus share same functions without implementing again.

Tested=On OCP Deltalake, dmidecode -t 4 shows expected info.

Signed-off-by: JingleHsuWiwynn <jingle_hsu@wiwynn.com>
Change-Id: I17df8de67bc2f5e89ea04da36efb2480a7e73174
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
This commit is contained in:
JingleHsuWiwynn 2021-10-07 10:45:47 +08:00 committed by Martin Roth
parent 323e5a84eb
commit 014901bd9b
2 changed files with 11 additions and 11 deletions
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11
src/mainboard/ocp/deltalake/ramstage.c
View File

@ -327,17 +327,6 @@ void smbios_fill_dimm_locator(const struct dimm_info *dimm, struct smbios_type17
t->bank_locator = smbios_add_string(t->eos, buf);
}
unsigned int smbios_processor_family(struct cpuid_result res)
{
return 0xb3; /* Xeon */
}
unsigned int smbios_processor_characteristics(void)
{
/* 64-bit Capable, Multi-Core, Power/Performance Control */
return 0x8c; /* BIT2 | BIT3 | BIT7 */
}
static void mainboard_enable(struct device *dev)
{
dev->ops->get_smbios_strings = dl_oem_smbios_strings;

11
src/soc/intel/xeon_sp/ramstage.c
View File

@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <cpu/cpu.h>
#include <smbios.h>
unsigned int smbios_cache_error_correction_type(u8 level)
@ -24,3 +25,13 @@ unsigned int smbios_cache_conf_operation_mode(u8 level)
return SMBIOS_CACHE_OP_MODE_UNKNOWN;
}
}
unsigned int smbios_processor_family(struct cpuid_result res)
{
return SMBIOS_PROCESSOR_FAMILY_XEON;
}
unsigned int smbios_processor_characteristics(void)
{
return PROCESSOR_64BIT_CAPABLE|PROCESSOR_MULTI_CORE|PROCESSOR_POWER_PERFORMANCE_CONTROL;
}