diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index b1ffcb2fe8..7014a2e60b 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -97,6 +97,9 @@ struct soc_intel_skylake_config {
 	/* TCC activation offset */
 	int tcc_offset;
 
+	/* Package PL4 power limit in Watts */
+	u32 PowerLimit4;
+
 	/* PL2 Override value in Watts */
 	u32 tdp_pl2_override;
 	/* PL1 Override value in Watts */
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 8a78348794..18c2aef676 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -369,6 +369,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 
 	tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi;
 	tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock;
+	tconfig->PowerLimit4 = config->PowerLimit4;
 	/*
 	 * To disable HECI, the Psf needs to be left unlocked
 	 * by FSP till end of post sequence. Based on the devicetree