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soc/intel/skylake: Use LPSS common library 

Use lpss common library to program reset and
clock register for lpss modules.

Change-Id: I198feba7c6f6d033ab77ed25a5bd9ea99411a1e4
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/19153
Tested-by: build bot (Jenkins)
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Aamir Bohra 2017-04-06 11:15:18 +05:30 committed by Martin Roth
parent ccfea16cd4
commit 015c64335d
4 changed files with 11 additions and 30 deletions
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1
src/soc/intel/skylake/Kconfig
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@ -51,6 +51,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_GSPI
select SOC_INTEL_COMMON_BLOCK_LPSS
select SOC_INTEL_COMMON_BLOCK_PCR
select SOC_INTEL_COMMON_BLOCK_RTC
select SOC_INTEL_COMMON_BLOCK_SA

10
src/soc/intel/skylake/bootblock/i2c.c
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@ -18,11 +18,11 @@
#include <device/device.h>
#include <device/i2c.h>
#include <device/pci_def.h>
#include <intelblocks/lpss.h>
#include <soc/intel/common/lpss_i2c.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include <soc/bootblock.h>
#include <soc/serialio.h>
#include "chip.h"
uintptr_t lpss_i2c_base_address(unsigned int bus)
@ -49,8 +49,6 @@ static void i2c_early_init_bus(unsigned int bus)
pci_devfn_t dev;
int devfn;
uintptr_t base;
uint32_t value;
void *reg;
/* Find the PCI device for this bus controller */
devfn = i2c_bus_to_devfn(bus);
@ -77,11 +75,7 @@ static void i2c_early_init_bus(unsigned int bus)
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
/* Take device out of reset */
reg = (void *)(base + SIO_REG_PPR_RESETS);
value = read32(reg);
value |= SIO_REG_PPR_RESETS_FUNC | SIO_REG_PPR_RESETS_APB |
SIO_REG_PPR_RESETS_IDMA;
write32(reg, value);
lpss_reset_release(base);
/* Initialize the controller */
lpss_i2c_init(bus, &config->i2c[bus]);

19
src/soc/intel/skylake/bootblock/uart.c
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@ -18,12 +18,12 @@
#include <arch/io.h>
#include <console/uart.h>
#include <device/pci_def.h>
#include <intelblocks/lpss.h>
#include <intelblocks/pcr.h>
#include <stdint.h>
#include <soc/bootblock.h>
#include <soc/pci_devs.h>
#include <soc/pcr_ids.h>
#include <soc/serialio.h>
#include <gpio.h>
/* Serial IO UART controller legacy mode */
@ -32,6 +32,10 @@
#define PCR_SIO_PCH_LEGACY_UART1 (1 << 1)
#define PCR_SIO_PCH_LEGACY_UART2 (1 << 2)
/* Clock divider parameters for 115200 baud rate */
#define CLOCK_DIV_M_VAL 0x30
#define CLOCK_DIV_N_VAL 0xc35
/* UART2 pad configuration. Support RXD and TXD for now. */
static const struct pad_config uart2_pads[] = {
/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
@ -42,7 +46,7 @@ void pch_uart_init(void)
{
device_t dev = PCH_DEV_UART2;
u32 tmp;
u8 *base = (void *)uart_platform_base(CONFIG_UART_FOR_CONSOLE);
uintptr_t base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
/* Set configured UART2 base address */
pci_write_config32(dev, PCI_BASE_ADDRESS_0, (u32)base);
@ -53,21 +57,14 @@ void pch_uart_init(void)
pci_write_config32(dev, PCI_COMMAND, tmp);
/* Take UART2 out of reset */
tmp = read32(base + SIO_REG_PPR_RESETS);
tmp |= SIO_REG_PPR_RESETS_FUNC | SIO_REG_PPR_RESETS_APB |
SIO_REG_PPR_RESETS_IDMA;
write32(base + SIO_REG_PPR_RESETS, tmp);
lpss_reset_release(base);
/*
* Set M and N divisor inputs and enable clock.
* Main reference frequency to UART is:
* 120MHz * M / N = 120MHz * 48 / 3125 = 1843200Hz
*/
tmp = read32(base + SIO_REG_PPR_CLOCK);
tmp |= SIO_REG_PPR_CLOCK_EN | SIO_REG_PPR_CLOCK_UPDATE |
(SIO_REG_PPR_CLOCK_N_DIV << 16) |
(SIO_REG_PPR_CLOCK_M_DIV << 1);
write32(base + SIO_REG_PPR_CLOCK, tmp);
lpss_clk_update(base, CLOCK_DIV_M_VAL, CLOCK_DIV_N_VAL);
/* Put UART2 in byte access mode for 16550 compatibility */
if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32))

11
src/soc/intel/skylake/include/soc/serialio.h
View File

@ -17,17 +17,6 @@
#ifndef _SERIALIO_H_
#define _SERIALIO_H_
#define SIO_REG_PPR_CLOCK 0x200
#define SIO_REG_PPR_CLOCK_EN (1 << 0)
#define SIO_REG_PPR_CLOCK_UPDATE (1 << 31)
#define SIO_REG_PPR_CLOCK_N_DIV 0xc35
#define SIO_REG_PPR_CLOCK_M_DIV 0x30
#define SIO_REG_PPR_RESETS 0x204
#define SIO_REG_PPR_RESETS_FUNC (1 << 0)
#define SIO_REG_PPR_RESETS_APB (1 << 1)
#define SIO_REG_PPR_RESETS_IDMA (1 << 2)
typedef enum {
PchSerialIoDisabled,
PchSerialIoAcpi,