sb/intel/i82801jx: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB

Use common code to detect ACPI S3.

Untested.

Change-Id: I2264c087b317f70506817b5458295a17e83b1efc
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32038
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/asus/p5qc/romstage.c

@@ -18,6 +18,7 @@
 #include <console/console.h>
 #include <southbridge/intel/i82801jx/i82801jx.h>
 #include <southbridge/intel/common/gpio.h>
+#include <southbridge/intel/common/pmclib.h>
 #include <northbridge/intel/x4x/x4x.h>
 #include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>

src/mainboard/intel/dg43gt/romstage.c

@@ -18,6 +18,7 @@
 #include <console/console.h>
 #include <southbridge/intel/i82801jx/i82801jx.h>
 #include <southbridge/intel/common/gpio.h>
+#include <southbridge/intel/common/pmclib.h>
 #include <northbridge/intel/x4x/x4x.h>
 #include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>

src/southbridge/intel/i82801jx/Kconfig

@@ -20,6 +20,7 @@ config SOUTHBRIDGE_INTEL_I82801JX
 	select SOUTHBRIDGE_INTEL_COMMON_SMBUS
 	select SOUTHBRIDGE_INTEL_COMMON_SPI
 	select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
+	select SOUTHBRIDGE_INTEL_COMMON_PMCLIB
 	select IOAPIC
 	select HAVE_USBDEBUG
 	select USE_WATCHDOG_ON_BOOT

src/southbridge/intel/i82801jx/Makefile.inc

@@ -34,6 +34,5 @@ ramstage-y += ../i82801gx/watchdog.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
 
 romstage-y += early_smbus.c
-romstage-y += early_lpc.c
 
 endif

src/southbridge/intel/i82801jx/early_lpc.c

@@ -1,43 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <console/console.h>
-#include <arch/acpi.h>
-#include "i82801jx.h"
-
-int southbridge_detect_s3_resume(void)
-{
-	u32 reg32;
-
-	/* Read PM1_CNT */
-	reg32 = inl(DEFAULT_PMBASE + 0x04);
-	printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
-	if (((reg32 >> 10) & 7) == 5) {
-		if (!acpi_s3_resume_allowed()) {
-			printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
-		} else {
-			printk(BIOS_DEBUG, "Resume from S3 detected.\n");
-			/* Clear SLP_TYPE. This will break stage2 but
-			 * we care for that when we get there.
-			 */
-			outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
-			return 1;
-		}
-	}
-
-	return 0;
-}

src/southbridge/intel/i82801jx/i82801jx.h

@@ -240,7 +240,6 @@ int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes,
 int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf);
 int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes,
 		const u8 *buf);
-int southbridge_detect_s3_resume(void);
 #endif
 
 #endif