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soc/amd/common: Remove eSPI decode workaround 

We no longer lock up if we clear the port 80 bit. I'm assuming this was
fixed when we configured the PSP to no longer setup eSPI.

BUG=b:183974365
TEST=Boot guybrush to OS

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1530d08974d42e0b06eb783521dea32fca752d85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Raul E Rangel 2021-04-26 13:52:38 -06:00 committed by Martin Roth
parent 5db62ef94a
commit 01792e353b
1 changed files with 1 additions and 5 deletions
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6
src/soc/amd/common/block/lpc/espi_util.c
View File

@ -103,11 +103,7 @@ static void espi_clear_decodes(void)
unsigned int idx; unsigned int idx;
/* First turn off all enable bits, then zero base, range, and size registers */ /* First turn off all enable bits, then zero base, range, and size registers */
/* espi_write16(ESPI_DECODE, 0);
* There is currently a bug where the SMU will lock up at times if the port80h enable
* bit is cleared. See b/183974365
*/
espi_write16(ESPI_DECODE, (espi_read16(ESPI_DECODE) & ESPI_DECODE_IO_0x80_EN));
for (idx = 0; idx < ESPI_GENERIC_IO_WIN_COUNT; idx++) { for (idx = 0; idx < ESPI_GENERIC_IO_WIN_COUNT; idx++) {
espi_write16(ESPI_IO_RANGE_BASE(idx), 0); espi_write16(ESPI_IO_RANGE_BASE(idx), 0);