pcengines/apu1: Add switch between UART and GPIO modes

These are alternative customer options connected to J19 header.
We need to avoid modifying devicetree.cb, so we fix devicetree
for the super-io device-enables at runtime instead.

Change-Id: I04a79974b9bdf52b09ffc1b1362e201eab1ee011
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10178
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Kyösti Mälkki 2015-05-11 22:53:19 +03:00
parent 58d5e21851
commit 017c2150d4
3 changed files with 61 additions and 1 deletions

View File

@ -82,4 +82,34 @@ config DRIVERS_PS2_KEYBOARD
bool
default n
choice
prompt "J19 pins 1-10"
default PINMUX_OFF_C
config PINMUX_OFF_C
bool "disable"
config PINMUX_GPIO0
bool "GPIO"
config PINMUX_UART_C
bool "UART 0x3e8"
endchoice
choice
prompt "J19 pins 11-20"
default PINMUX_OFF_D
config PINMUX_OFF_D
bool "disable"
config PINMUX_GPIO1
bool "GPIO"
config PINMUX_UART_D
bool "UART 0x2e8"
endchoice
endif # BOARD_PCENGINES_APU1

View File

@ -59,16 +59,19 @@ chip northbridge/amd/agesa/family14/root_complex
irq 0x70 = 3
end
device pnp 2e.10 off
# UART C is conditionally turned on
io 0x60 = 0x3e8
irq 0x70 = 4
end
device pnp 2e.11 off
# UART D is conditionally turned on
io 0x60 = 0x2e8
irq 0x70 = 3
end
device pnp 2e.8 off end
device pnp 2e.f off end
device pnp 2e.7 off end
# GPIO0 and GPIO1 are conditionally turned on
device pnp 2e.007 off end
device pnp 2e.107 off end
device pnp 2e.607 off end
device pnp 2e.e off end

View File

@ -33,6 +33,7 @@
#include "SBPLATFORM.h"
#include <southbridge/amd/cimx/sb800/pci_devs.h>
#include <northbridge/amd/agesa/family14/pci_devs.h>
#include <superio/nuvoton/nct5104d/nct5104d.h>
#include "gpio_ftns.h"
void set_pcie_reset(void);
@ -135,6 +136,30 @@ static void pirq_setup(void)
picr_data_ptr = mainboard_picr_data;
}
/* Wrapper to enable GPIO/UART devices under menuconfig. Revisit
* once configuration file format for SPI flash storage is complete.
*/
#define SIO_PORT 0x2e
static void config_gpio_mux(void)
{
struct device *uart, *gpio;
uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3);
gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO0);
if (uart)
uart->enabled = CONFIG_PINMUX_UART_C;
if (gpio)
gpio->enabled = CONFIG_PINMUX_GPIO0;
uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4);
gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO1);
if (uart)
uart->enabled = CONFIG_PINMUX_UART_D;
if (gpio)
gpio->enabled = CONFIG_PINMUX_GPIO1;
}
/**
* TODO
* SB CIMx callback
@ -158,6 +183,8 @@ static void mainboard_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
config_gpio_mux();
/* Initialize the PIRQ data structures for consumption */
pirq_setup();
}