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cpu/amd/pi: Fix checkpatch warnings and errors 

Fix remaining space prohibited between function name and open
parenthesis, line over 80 characters, unnecessary braces for single
statement blocks, space required before open brace errors and warnings
in subdirectories of src/cpu/amd/pi

Change-Id: I177ffe98a3674bd700a39eb8073db34adf9499b4
Signed-off-by: Evelyn Huang <evhuang@google.com>
Reviewed-on: https://review.coreboot.org/20098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Evelyn Huang 2017-06-07 14:20:09 -06:00 committed by Stefan Reinauer
parent 67ce5052fe
commit 0182aea283
5 changed files with 65 additions and 55 deletions
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17
src/cpu/amd/pi/00660F01/fixme.c
View File

@ -34,11 +34,14 @@ void amd_initcpuio(void)
* set to non-posted regions. * set to non-posted regions.
*/ */
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84); PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84);
PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */ /* last address before processor local APIC at FEE00000 */
PciData |= 1 << 7; /* set NP (non-posted) bit */ PciData = 0x00FEDF00;
/* set NP (non-posted) bit */
PciData |= 1 << 7;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80); PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */ /* lowest NP address is HPET at FED00000 */
PciData = (0xFED00000 >> 8) | 3;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Map the remaining PCI hole as posted MMIO */ /* Map the remaining PCI hole as posted MMIO */
@ -68,10 +71,12 @@ void amd_initmmio(void)
AMD_CONFIG_PARAMS StdHeader; AMD_CONFIG_PARAMS StdHeader;
/* /*
Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base * Set the MMIO Configuration Base Address and
Address MSR register. * Bus Range onto MMIO configuration base
* Address MSR register.
*/ */
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; MsrReg = CONFIG_MMCONF_BASE_ADDRESS |
(LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader); LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
/* For serial port */ /* For serial port */

3
src/cpu/amd/pi/00660F01/model_15_init.c
View File

@ -85,9 +85,8 @@ static void model_15_init(device_t dev)
/* zero the machine check error status registers */ /* zero the machine check error status registers */
msr.lo = 0; msr.lo = 0;
msr.hi = 0; msr.hi = 0;
for (i = 0; i < 6; i++) { for (i = 0; i < 6; i++)
wrmsr(MCI_STATUS + (i * 4), msr); wrmsr(MCI_STATUS + (i * 4), msr);
}
/* Enable the local CPU APICs */ /* Enable the local CPU APICs */

17
src/cpu/amd/pi/00730F01/fixme.c
View File

@ -34,11 +34,14 @@ void amd_initcpuio(void)
* set to non-posted regions. * set to non-posted regions.
*/ */
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84); PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84);
PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */ /* last address before processor local APIC at FEE00000 */
PciData |= 1 << 7; /* set NP (non-posted) bit */ PciData = 0x00FEDF00;
/* set NP (non-posted) bit */
PciData |= 1 << 7;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80); PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */ /* lowest NP address is HPET at FED00000 */
PciData = (0xFED00000 >> 8) | 3;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Map the remaining PCI hole as posted MMIO */ /* Map the remaining PCI hole as posted MMIO */
@ -68,10 +71,12 @@ void amd_initmmio(void)
AMD_CONFIG_PARAMS StdHeader; AMD_CONFIG_PARAMS StdHeader;
/* /*
Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base * Set the MMIO Configuration Base Address and
Address MSR register. * Bus Range onto MMIO configuration base
* Address MSR register.
*/ */
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; MsrReg = CONFIG_MMCONF_BASE_ADDRESS |
(LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader); LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
/* For serial port */ /* For serial port */

7
src/cpu/amd/pi/00730F01/model_16_init.c
View File

@ -48,7 +48,9 @@ static void model_16_init(device_t dev)
msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn;
wrmsr(SYSCFG_MSR, msr); wrmsr(SYSCFG_MSR, msr);
// BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs /* BSP: make a0000-bffff UC, c0000-fffff WB,
* same as OntarioApMtrrSettingsList for APs
*/
msr.lo = msr.hi = 0; msr.lo = msr.hi = 0;
wrmsr(0x259, msr); wrmsr(0x259, msr);
msr.lo = msr.hi = 0x1e1e1e1e; msr.lo = msr.hi = 0x1e1e1e1e;
@ -68,9 +70,8 @@ static void model_16_init(device_t dev)
/* zero the machine check error status registers */ /* zero the machine check error status registers */
msr.lo = 0; msr.lo = 0;
msr.hi = 0; msr.hi = 0;
for (i = 0; i < 6; i++) { for (i = 0; i < 6; i++)
wrmsr(MCI_STATUS + (i * 4), msr); wrmsr(MCI_STATUS + (i * 4), msr);
}
/* Enable the local CPU APICs */ /* Enable the local CPU APICs */