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nb/intel/sandybridge/raminit: Add shift offset 

It looks like the falling timing was missing the shift offset.
Not sure if this was intentional, I guess not.

Tested on my hardware and produced no regressions.

Test system:
 * Intel IvyBridge
 * Gigabyte GA-B75M-D3H

Please test on real hardware !

Change-Id: Id8c60217093a48bf322f406ea258c10a02c936e8
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13682
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Patrick Rudolph 2016-02-10 19:16:34 +01:00 committed by Martin Roth
parent 44ef167d21
commit 0188b1399a
1 changed files with 2 additions and 2 deletions
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4
src/northbridge/intel/sandybridge/raminit.c
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@ -1607,8 +1607,8 @@ static void program_timings(ramctr_timing * ctrl, int channel)
(((ctrl->timings[channel][slotrank].lanes[lane]. (((ctrl->timings[channel][slotrank].lanes[lane].
timA + shift - timA + shift -
(post_timA_min_high << 6)) & 0x1c0) << 10) (post_timA_min_high << 6)) & 0x1c0) << 10)
| (ctrl->timings[channel][slotrank].lanes[lane]. | ((ctrl->timings[channel][slotrank].lanes[lane].
falling << 20)); falling + shift) << 20));
MCHBAR32(lane_registers[lane] + 0x20 + 0x100 * channel + MCHBAR32(lane_registers[lane] + 0x20 + 0x100 * channel +
4 * slotrank) 4 * slotrank)