arch/riscv: Don't hardcode CSR numbers anymore
They are hopefully stable enough by now. TEST=Building with for emulation/spike-riscv with BUILD_TIMELESS, with and without this patch, results in the same coreboot.rom. Change-Id: Ie6747c7eeea6cd8fd2138c5ba535a08c5add9038 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/30164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Philipp Hug <philipp@hug.cx>
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@ -59,11 +59,6 @@ void mstatus_init(void)
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set_csr(medeleg, delegate);
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}
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// Enable all user/supervisor-mode counters using
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// v1.10 register addresses.
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// They moved from the earlier spec.
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// Until we trust our toolchain use the hardcoded constants.
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// These were in flux and people who get the older toolchain
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// will have difficult-to-debug failures.
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write_csr(/*mcounteren*/0x306, 7);
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// Enable all user/supervisor-mode counters
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write_csr(mcounteren, 7);
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}
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