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- Update abuild.sh so it will rebuild successfull builds 

- Move pci_set_method out of hardwaremain.c
- Re-add debugging name field but only include the CONFIG_CHIP_NAME is
  enabled.  All instances are now wrapped in CHIP_NAME
- Many minor cleanups so most ports build.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1737 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Eric Biederman 2004-11-04 11:04:33 +00:00
parent 4403f60823
commit 018d8dd60f
116 changed files with 1397 additions and 3197 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
documentation/LinuxBIOS-AMD64.tex
View File

@ -551,13 +551,14 @@ do:
\begin{verbatim}
makerule ./auto.E
depends "$(MAINBOARD)/auto.c"
action "$(CPP) ­I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) \
$(MAINBOARD)/auto.c > ./auto.E"
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -E -mcpu=k8 -O2 ­I$(TOP)/src -I. $(CPPFLAGS) \
$(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "./auto.E ./romcc"
action "./romcc ­mcpu=k8 ­O ./auto.E > auto.inc"
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -mcpu=k8 -O2 ­I$(TOP)/src -I. $(CPPFLAGS) \
$(MAINBOARD)/auto.c -o $@"
end
\end{verbatim}

18
src/arch/i386/include/arch/pci_ops.h Normal file
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@ -0,0 +1,18 @@
#ifndef ARCH_I386_PCI_OPS_H
#define ARCH_I386_PCI_OPS_H
struct pci_ops {
uint8_t (*read8) (uint8_t bus, int devfn, int where);
uint16_t (*read16) (uint8_t bus, int devfn, int where);
uint32_t (*read32) (uint8_t bus, int devfn, int where);
void (*write8) (uint8_t bus, int devfn, int where, uint8_t val);
void (*write16) (uint8_t bus, int devfn, int where, uint16_t val);
void (*write32) (uint8_t bus, int devfn, int where, uint32_t val);
};
extern const struct pci_ops *conf;
void pci_set_method_conf1(void);
void pci_set_method_conf2(void);
void pci_set_method(void);
#endif /* ARCH_I386_PCI_OPS_H */

3
src/arch/i386/lib/Config.lb
View File

@ -7,4 +7,7 @@
object c_start.S
object cpu.c
object pci_ops.c
object pci_ops_conf1.c
object pci_ops_conf2.c
object pci_ops_auto.c
object exception.c

218
src/arch/i386/lib/pci_ops.c
View File

@ -5,218 +5,12 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
static const struct pci_ops *conf;
struct pci_ops {
uint8_t (*read8) (uint8_t bus, int devfn, int where);
uint16_t (*read16) (uint8_t bus, int devfn, int where);
uint32_t (*read32) (uint8_t bus, int devfn, int where);
void (*write8) (uint8_t bus, int devfn, int where, uint8_t val);
void (*write16) (uint8_t bus, int devfn, int where, uint16_t val);
void (*write32) (uint8_t bus, int devfn, int where, uint32_t val);
};
const struct pci_ops *conf = 0;
/*
* Direct access to PCI hardware...
*/
/*
* Functions for accessing PCI configuration space with type 1 accesses
*/
#define CONFIG_CMD(bus,devfn, where) (0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3))
static uint8_t pci_conf1_read_config8(unsigned char bus, int devfn, int where)
{
outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
return inb(0xCFC + (where & 3));
}
static uint16_t pci_conf1_read_config16(unsigned char bus, int devfn, int where)
{
outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
return inw(0xCFC + (where & 2));
}
static uint32_t pci_conf1_read_config32(unsigned char bus, int devfn, int where)
{
outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
return inl(0xCFC);
}
static void pci_conf1_write_config8(unsigned char bus, int devfn, int where, uint8_t value)
{
outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
outb(value, 0xCFC + (where & 3));
}
static void pci_conf1_write_config16(unsigned char bus, int devfn, int where, uint16_t value)
{
outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
outw(value, 0xCFC + (where & 2));
}
static void pci_conf1_write_config32(unsigned char bus, int devfn, int where, uint32_t value)
{
outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
outl(value, 0xCFC);
}
#undef CONFIG_CMD
static const struct pci_ops pci_direct_conf1 =
{
.read8 = pci_conf1_read_config8,
.read16 = pci_conf1_read_config16,
.read32 = pci_conf1_read_config32,
.write8 = pci_conf1_write_config8,
.write16 = pci_conf1_write_config16,
.write32 = pci_conf1_write_config32,
};
/*
* Functions for accessing PCI configuration space with type 2 accesses
*/
#define IOADDR(devfn, where) ((0xC000 | ((devfn & 0x78) << 5)) + where)
#define FUNC(devfn) (((devfn & 7) << 1) | 0xf0)
#define SET(bus,devfn) outb(FUNC(devfn), 0xCF8); outb(bus, 0xCFA);
static uint8_t pci_conf2_read_config8(unsigned char bus, int devfn, int where)
{
uint8_t value;
SET(bus, devfn);
value = inb(IOADDR(devfn, where));
outb(0, 0xCF8);
return value;
}
static uint16_t pci_conf2_read_config16(unsigned char bus, int devfn, int where)
{
uint16_t value;
SET(bus, devfn);
value = inw(IOADDR(devfn, where));
outb(0, 0xCF8);
return value;
}
static uint32_t pci_conf2_read_config32(unsigned char bus, int devfn, int where)
{
uint32_t value;
SET(bus, devfn);
value = inl(IOADDR(devfn, where));
outb(0, 0xCF8);
return value;
}
static void pci_conf2_write_config8(unsigned char bus, int devfn, int where, uint8_t value)
{
SET(bus, devfn);
outb(value, IOADDR(devfn, where));
outb(0, 0xCF8);
}
static void pci_conf2_write_config16(unsigned char bus, int devfn, int where, uint16_t value)
{
SET(bus, devfn);
outw(value, IOADDR(devfn, where));
outb(0, 0xCF8);
}
static void pci_conf2_write_config32(unsigned char bus, int devfn, int where, uint32_t value)
{
SET(bus, devfn);
outl(value, IOADDR(devfn, where));
outb(0, 0xCF8);
}
#undef SET
#undef IOADDR
#undef FUNC
static const struct pci_ops pci_direct_conf2 =
{
.read8 = pci_conf2_read_config8,
.read16 = pci_conf2_read_config16,
.read32 = pci_conf2_read_config32,
.write8 = pci_conf2_write_config8,
.write16 = pci_conf2_write_config16,
.write32 = pci_conf2_write_config32,
};
/*
* Before we decide to use direct hardware access mechanisms, we try to do some
* trivial checks to ensure it at least _seems_ to be working -- we just test
* whether bus 00 contains a host bridge (this is similar to checking
* techniques used in XFree86, but ours should be more reliable since we
* attempt to make use of direct access hints provided by the PCI BIOS).
*
* This should be close to trivial, but it isn't, because there are buggy
* chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
*/
static int pci_sanity_check(const struct pci_ops *o)
{
uint16_t class, vendor;
uint8_t bus;
int devfn;
#define PCI_CLASS_BRIDGE_HOST 0x0600
#define PCI_CLASS_DISPLAY_VGA 0x0300
#define PCI_VENDOR_ID_COMPAQ 0x0e11
#define PCI_VENDOR_ID_INTEL 0x8086
#define PCI_VENDOR_ID_MOTOROLA 0x1057
for (bus = 0, devfn = 0; devfn < 0x100; devfn++) {
class = o->read16(bus, devfn, PCI_CLASS_DEVICE);
vendor = o->read16(bus, devfn, PCI_VENDOR_ID);
if (((class == PCI_CLASS_BRIDGE_HOST) || (class == PCI_CLASS_DISPLAY_VGA)) ||
((vendor == PCI_VENDOR_ID_INTEL) || (vendor == PCI_VENDOR_ID_COMPAQ) ||
(vendor == PCI_VENDOR_ID_MOTOROLA))) {
return 1;
}
}
printk_err("PCI: Sanity check failed\n");
return 0;
}
static const struct pci_ops *pci_check_direct(void)
{
unsigned int tmp;
/*
* Check if configuration type 1 works.
*/
{
outb(0x01, 0xCFB);
tmp = inl(0xCF8);
outl(0x80000000, 0xCF8);
if (inl(0xCF8) == 0x80000000 &&
pci_sanity_check(&pci_direct_conf1)) {
outl(tmp, 0xCF8);
printk_debug("PCI: Using configuration type 1\n");
return &pci_direct_conf1;
}
outl(tmp, 0xCF8);
}
/*
* Check if configuration type 2 works.
*/
{
outb(0x00, 0xCFB);
outb(0x00, 0xCF8);
outb(0x00, 0xCFA);
if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00 &&
pci_sanity_check(&pci_direct_conf2)) {
printk_debug("PCI: Using configuration type 2\n");
return &pci_direct_conf2;
}
}
printk_debug("pci_check_direct failed\n");
return 0;
}
uint8_t pci_read_config8(device_t dev, unsigned where)
{
uint8_t value;
@ -264,13 +58,3 @@ void pci_write_config32(device_t dev, unsigned where, uint32_t val)
dev->bus->secondary, dev->path.u.pci.devfn, where, val);
conf->write32(dev->bus->secondary, dev->path.u.pci.devfn, where, val);
}
/** Set the method to be used for PCI, type I or type II
*/
void pci_set_method(void)
{
conf = &pci_direct_conf1;
conf = pci_check_direct();
}

92
src/arch/i386/lib/pci_ops_auto.c Normal file
View File

@ -0,0 +1,92 @@
#include <console/console.h>
#include <arch/io.h>
#include <arch/pciconf.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
/*
* Before we decide to use direct hardware access mechanisms, we try to do some
* trivial checks to ensure it at least _seems_ to be working -- we just test
* whether bus 00 contains a host bridge (this is similar to checking
* techniques used in XFree86, but ours should be more reliable since we
* attempt to make use of direct access hints provided by the PCI BIOS).
*
* This should be close to trivial, but it isn't, because there are buggy
* chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
*/
static int pci_sanity_check(const struct pci_ops *o)
{
uint16_t class, vendor;
uint8_t bus;
int devfn;
#define PCI_CLASS_BRIDGE_HOST 0x0600
#define PCI_CLASS_DISPLAY_VGA 0x0300
#define PCI_VENDOR_ID_COMPAQ 0x0e11
#define PCI_VENDOR_ID_INTEL 0x8086
#define PCI_VENDOR_ID_MOTOROLA 0x1057
for (bus = 0, devfn = 0; devfn < 0x100; devfn++) {
class = o->read16(bus, devfn, PCI_CLASS_DEVICE);
vendor = o->read16(bus, devfn, PCI_VENDOR_ID);
if (((class == PCI_CLASS_BRIDGE_HOST) || (class == PCI_CLASS_DISPLAY_VGA)) ||
((vendor == PCI_VENDOR_ID_INTEL) || (vendor == PCI_VENDOR_ID_COMPAQ) ||
(vendor == PCI_VENDOR_ID_MOTOROLA))) {
return 1;
}
}
printk_err("PCI: Sanity check failed\n");
return 0;
}
static void pci_check_direct(void)
{
unsigned int tmp;
/*
* Check if configuration type 1 works.
*/
{
outb(0x01, 0xCFB);
tmp = inl(0xCF8);
outl(0x80000000, 0xCF8);
if (inl(0xCF8) == 0x80000000) {
pci_set_method_conf1();
if (pci_sanity_check(conf)) {
outl(tmp, 0xCF8);
printk_debug("PCI: Using configuration type 1\n");
return;
}
}
outl(tmp, 0xCF8);
}
/*
* Check if configuration type 2 works.
*/
{
outb(0x00, 0xCFB);
outb(0x00, 0xCF8);
outb(0x00, 0xCFA);
if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00) {
pci_set_method_conf2();
if (pci_sanity_check(conf)) {
printk_debug("PCI: Using configuration type 2\n");
}
}
}
printk_debug("pci_check_direct failed\n");
conf = 0;
return;
}
/** Set the method to be used for PCI, type I or type II
*/
void pci_set_method(void)
{
printk_info("Finding PCI configuration type.\n");
pci_check_direct();
post_code(0x5f);
}

64
src/arch/i386/lib/pci_ops_conf1.c Normal file
View File

@ -0,0 +1,64 @@
#include <console/console.h>
#include <arch/io.h>
#include <arch/pciconf.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
/*
* Functions for accessing PCI configuration space with type 1 accesses
*/
#define CONFIG_CMD(bus,devfn, where) (0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3))
static uint8_t pci_conf1_read_config8(unsigned char bus, int devfn, int where)
{
outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
return inb(0xCFC + (where & 3));
}
static uint16_t pci_conf1_read_config16(unsigned char bus, int devfn, int where)
{
outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
return inw(0xCFC + (where & 2));
}
static uint32_t pci_conf1_read_config32(unsigned char bus, int devfn, int where)
{
outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
return inl(0xCFC);
}
static void pci_conf1_write_config8(unsigned char bus, int devfn, int where, uint8_t value)
{
outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
outb(value, 0xCFC + (where & 3));
}
static void pci_conf1_write_config16(unsigned char bus, int devfn, int where, uint16_t value)
{
outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
outw(value, 0xCFC + (where & 2));
}
static void pci_conf1_write_config32(unsigned char bus, int devfn, int where, uint32_t value)
{
outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
outl(value, 0xCFC);
}
#undef CONFIG_CMD
static const struct pci_ops pci_direct_conf1 =
{
.read8 = pci_conf1_read_config8,
.read16 = pci_conf1_read_config16,
.read32 = pci_conf1_read_config32,
.write8 = pci_conf1_write_config8,
.write16 = pci_conf1_write_config16,
.write32 = pci_conf1_write_config32,
};
void pci_set_method_conf1(void)
{
conf = &pci_direct_conf1;
}

80
src/arch/i386/lib/pci_ops_conf2.c Normal file
View File

@ -0,0 +1,80 @@
#include <console/console.h>
#include <arch/io.h>
#include <arch/pciconf.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
/*
* Functions for accessing PCI configuration space with type 2 accesses
*/
#define IOADDR(devfn, where) ((0xC000 | ((devfn & 0x78) << 5)) + where)
#define FUNC(devfn) (((devfn & 7) << 1) | 0xf0)
#define SET(bus,devfn) outb(FUNC(devfn), 0xCF8); outb(bus, 0xCFA);
static uint8_t pci_conf2_read_config8(unsigned char bus, int devfn, int where)
{
uint8_t value;
SET(bus, devfn);
value = inb(IOADDR(devfn, where));
outb(0, 0xCF8);
return value;
}
static uint16_t pci_conf2_read_config16(unsigned char bus, int devfn, int where)
{
uint16_t value;
SET(bus, devfn);
value = inw(IOADDR(devfn, where));
outb(0, 0xCF8);
return value;
}
static uint32_t pci_conf2_read_config32(unsigned char bus, int devfn, int where)
{
uint32_t value;
SET(bus, devfn);
value = inl(IOADDR(devfn, where));
outb(0, 0xCF8);
return value;
}
static void pci_conf2_write_config8(unsigned char bus, int devfn, int where, uint8_t value)
{
SET(bus, devfn);
outb(value, IOADDR(devfn, where));
outb(0, 0xCF8);
}
static void pci_conf2_write_config16(unsigned char bus, int devfn, int where, uint16_t value)
{
SET(bus, devfn);
outw(value, IOADDR(devfn, where));
outb(0, 0xCF8);
}
static void pci_conf2_write_config32(unsigned char bus, int devfn, int where, uint32_t value)
{
SET(bus, devfn);
outl(value, IOADDR(devfn, where));
outb(0, 0xCF8);
}
#undef SET
#undef IOADDR
#undef FUNC
static const struct pci_ops pci_direct_conf2 =
{
.read8 = pci_conf2_read_config8,
.read16 = pci_conf2_read_config16,
.read32 = pci_conf2_read_config32,
.write8 = pci_conf2_write_config8,
.write16 = pci_conf2_write_config16,
.write32 = pci_conf2_write_config32,
};
void pci_set_method_conf2(void)
{
conf = &pci_direct_conf2;
}

6
src/arch/ppc/include/arch/pci_ops.h Normal file
View File

@ -0,0 +1,6 @@
#ifndef ARCH_I386_PCI_OPS_H
#define ARCH_I386_PCI_OPS_H
void pci_set_method(void);
#endif /* ARCH_I386_PCI_OPS_H */

14
src/boot/hardwaremain.c
View File

@ -69,21 +69,15 @@ void hardwaremain(int boot_complete)
/* FIXME: Is there a better way to handle this? */
init_timer();
/* pick how to scan the bus. This is first so we can get at memory size. */
printk_info("Finding PCI configuration type.\n");
pci_set_method();
post_code(0x5f);
/* Find the devices we don't have hard coded knowledge about. */
dev_enumerate();
post_code(0x66);
/* Now do the real bus.
* We round the total ram up a lot for thing like the SISFB, which
* shares high memory with the CPU.
*/
/* Now compute and assign the bus resources. */
dev_configure();
post_code(0x88);
/* Now actually enable devices on the bus */
dev_enable();
/* And of course initialize devices on the bus */
dev_initialize();
post_code(0x89);

1
src/config/Config.lb
View File

@ -7,7 +7,6 @@ makedefine LIBGCC_FILE_NAME := $(shell $(CC) -print-libgcc-file-name)
makedefine GCC_INC_DIR := $(shell $(CC) -print-search-dirs | sed -ne "s/install: \(.*\)/\1include/gp")
makedefine CPPFLAGS := -I$(TOP)/src/include -I$(TOP)/src/arch/$(ARCH)/include -I$(GCC_INC_DIR) $(CPUFLAGS)
makedefine ROMCCPPFLAGS := -D__ROMCC__=0 -D__ROMCC_MINOR__=64
makedefine CFLAGS := $(CPU_OPT) $(CPPFLAGS) -Os -nostdinc -nostdlib -fno-builtin -Wall
makedefine HOSTCFLAGS:= -Os -Wall

6
src/config/Options.lb
View File

@ -677,6 +677,12 @@ end
# Misc options
###############################################
define CONFIG_CHIP_NAME
default 0
export always
comment "Compile in the chip name"
end
define CONFIG_GDB_STUB
default 0
export used

2
src/cpu/amd/socket_754/socket_754.c
View File

@ -3,5 +3,5 @@
struct chip_operations cpu_amd_socket_754_ops = {
.name = "socket 754",
CHIP_NAME("socket 754")
};

1
src/cpu/amd/socket_940/socket_940.c
View File

@ -3,4 +3,5 @@
struct chip_operations cpu_amd_socket_940_ops = {
CHIP_NAME("socket 940")
};

2
src/cpu/intel/slot_2/slot_2.c
View File

@ -3,5 +3,5 @@
struct chip_operations cpu_intel_slot_2_control = {
.name = "slot 2",
CHIP_NAME("slot 2")
};

2
src/cpu/intel/socket_mPGA479M/socket_mPGA479M.c
View File

@ -3,5 +3,5 @@
struct chip_opertations cpu_intel_socket_mPGA479M_control = {
.name = "socket mPGA479M",
CHIP_NAME("socket mPGA479M")
};

2
src/cpu/intel/socket_mPGA603/socket_mPGA603_400Mhz.c
View File

@ -3,5 +3,5 @@
struct chip_opertations cpu_intel_socket_mPGA603_control = {
.name = "socket mPGA603_400Mhz",
CHIP_NAME("socket mPGA603_400Mhz")
};

1
src/cpu/intel/socket_mPGA604_533Mhz/socket_mPGA604_533Mhz.c
View File

@ -3,4 +3,5 @@
struct chip_operations cpu_intel_socket_mPGA604_533Mhz_ops = {
CHIP_NAME("socket mPGA604_533Mhz")
};

2
src/cpu/intel/socket_mPGA604_800Mhz/socket_mPGA604_800Mhz.c
View File

@ -3,5 +3,5 @@
struct chip_operations cpu_intel_socket_mPGA604_800Mhz_control = {
.name = "socket mPGA604_800Mhz",
CHIP_NAME("socket mPGA604_800Mhz")
};

9
src/include/device/device.h
View File

@ -14,8 +14,17 @@ struct smbus_bus_operations;
/* Chip operations */
struct chip_operations {
void (*enable_dev)(struct device *dev);
#if CONFIG_CHIP_NAME == 1
char *name;
#endif
};
#if CONFIG_CHIP_NAME == 1
#define CHIP_NAME(X) .name = X,
#else
#define CHIP_NAME(X)
#endif
struct device_operations {
void (*read_resources)(device_t dev);
void (*set_resources)(device_t dev);

3
src/include/device/pci_ops.h
View File

@ -3,6 +3,7 @@
#include <stdint.h>
#include <device/device.h>
#include <arch/pci_ops.h>
uint8_t pci_read_config8(device_t dev, unsigned where);
uint16_t pci_read_config16(device_t dev, unsigned where);
@ -11,6 +12,4 @@ void pci_write_config8(device_t dev, unsigned where, uint8_t val);
void pci_write_config16(device_t dev, unsigned where, uint16_t val);
void pci_write_config32(device_t dev, unsigned where, uint32_t val);
void pci_set_method(void);
#endif /* PCI_OPS_H */

162
src/mainboard/Iwill/DK8S2/Config.lb
View File

@ -1,110 +1,3 @@
uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
uses HARD_RESET_BUS
uses HARD_RESET_DEVICE
uses HARD_RESET_FUNCTION
uses IRQ_SLOT_COUNT
uses HAVE_OPTION_TABLE
uses CONFIG_MAX_CPUS
uses CONFIG_IOAPIC
uses CONFIG_SMP
uses FALLBACK_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_ROM_STREAM
uses CONFIG_ROM_STREAM_START
uses PAYLOAD_SIZE
uses _ROMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses STACK_SIZE
uses HEAP_SIZE
uses USE_OPTION_TABLE
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE=524288
###
### Build options
###
##
## Build code for the fallback boot
##
default HAVE_FALLBACK_BOOT=1
##
## Build code to reset the motherboard from linuxBIOS
##
default HAVE_HARD_RESET=1
default HARD_RESET_BUS=1
default HARD_RESET_DEVICE=4
default HARD_RESET_FUNCTION=0
##
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=9
##
## Build code to export an x86 MP table
## Useful for specifying IRQ routing values
##
default HAVE_MP_TABLE=1
##
## Build code to export a CMOS option table
##
default HAVE_OPTION_TABLE=1
##
## Build code for SMP support
## Only worry about 2 micro processors
##
default CONFIG_SMP=1
default CONFIG_MAX_CPUS=2
##
## Build code to setup a generic IOAPIC
##
default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
#default MAINBOARD_PART_NUMBER="HDAMA"
#default MAINBOARD_VENDOR="ARIMA"
###
### LinuxBIOS layout values
###
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
default ROM_IMAGE_SIZE = 65536
##
## Use a small 8K stack
##
default STACK_SIZE=0x2000
##
## Use a small 16K heap
##
default HEAP_SIZE=0x4000
##
## Only use the option table in a normal image
##
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
##
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
@ -123,7 +16,6 @@ end
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_STREAM = 1
##
## Compute where this copy of linuxBIOS will start in the boot rom
@ -145,15 +37,12 @@ default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
##
arch i386 end
#cpu k8 end
##
## Build the objects we have code for in this directory.
##
#object mainboard.o
driver mainboard.o
#object static_devices.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
@ -164,41 +53,41 @@ dir /drivers/ati/ragexl
## Romcc output
##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
depends "./failover.E ./romcc"
action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c option_table.h"
action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "./auto.E ./romcc"
action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
##
mainboardinit cpu/i386/entry16.inc
mainboardinit cpu/i386/entry32.inc
ldscript /cpu/i386/entry16.lds
ldscript /cpu/i386/entry32.lds
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
##
## Build our reset vector (This is where linuxBIOS is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/i386/reset16.inc
ldscript /cpu/i386/reset16.lds
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
mainboardinit cpu/i386/reset32.inc
ldscript /cpu/i386/reset32.lds
mainboardinit cpu/x86/32bit/reset32.inc
ldscript /cpu/x86/32bit/reset32.lds
end
### Should this be in the northbridge code?
@ -210,11 +99,6 @@ mainboardinit arch/i386/lib/cpu_reset.inc
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
##
## Setup our mtrrs
##
mainboardinit cpu/k8/earlymtrr.inc
###
### This is the early phase of linuxBIOS startup
### Things are delicate and we test to see if we should
@ -232,9 +116,12 @@ end
##
## Setup RAM
##
mainboardinit cpu/k8/enable_mmx_sse.inc
mainboardinit cpu/x86/fpu/enable_fpu.inc
mainboardinit cpu/x86/mmx/enable_mmx.inc
mainboardinit cpu/x86/sse/enable_sse.inc
mainboardinit ./auto.inc
mainboardinit cpu/k8/disable_mmx_sse.inc
mainboardinit cpu/x86/sse/disable_sse.inc
mainboardinit cpu/x86/mmx/disable_mmx.inc
##
## Include the secondary Configuration files
@ -242,6 +129,7 @@ mainboardinit cpu/k8/disable_mmx_sse.inc
dir /pc80
config chip.h
# config for arima/hdama
chip northbridge/amd/amdk8
device pci_domain 0 on
device pci 18.0 on # LDT 0
@ -330,9 +218,3 @@ chip northbridge/amd/amdk8
end
end
##
## Include the old serial code for those few places that still need it.
##
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc

61
src/mainboard/Iwill/DK8S2/auto.c
View File

@ -2,10 +2,10 @@
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <cpu/p6/apic.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/smp/lapic.h>
#include <cpu/x86/lapic.h>
#include <arch/cpu.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
@ -14,19 +14,21 @@
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/k8/apic_timer.c"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#include "cpu/p6/boot_cpu.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
static void hard_reset(void)
{
set_bios_reset();
set_bios_reset();
/* enable cf9 */
pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
@ -40,6 +42,10 @@ static void soft_reset(void)
pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
}
/*
* GPIO28 of 8111 will control H0_MEMRESET_L
* GPIO29 of 8111 will control H1_MEMRESET_L
*/
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
@ -68,7 +74,7 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
/* Routing Table Node i
*
* F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
* i: 0, 1, 2, 3, 4, 5, 6, 7
* i: 0, 1, 2, 3, 4, 5, 6, 7
*
* [ 0: 3] Request Route
* [0] Route to this node
@ -124,12 +130,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#define FIRST_CPU 1
#define SECOND_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
static void main(void)
static void main(unsigned long bist)
{
/*
* GPIO28 of 8111 will control H0_MEMRESET_L
* GPIO29 of 8111 will control H1_MEMRESET_L
*/
static const struct mem_controller cpu[] = {
#if FIRST_CPU
{
@ -154,32 +156,39 @@ static void main(void)
},
#endif
};
int needs_reset;
enable_lapic();
init_timer();
if (cpu_init_detected()) {
asm("jmp __cpu_reset");
int needs_reset;
if (bist == 0) {
/* Skip this if there was a built in self test failure */
amd_early_mtrr_init();
enable_lapic();
init_timer();
/* Has this cpu already booted? */
if (cpu_init_detected()) {
asm volatile ("jmp __cpu_reset");
}
distinguish_cpu_resets();
if (!boot_cpu()) {
stop_this_cpu();
}
}
distinguish_cpu_resets();
if (!boot_cpu()) {
stop_this_cpu();
}
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
/* Setup the console */
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
setup_default_resource_map();
needs_reset = setup_coherent_ht_domain();
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
if (needs_reset) {
print_info("ht reset -\r\n");
soft_reset();
}
#if 0
print_pci_devices();
#endif

2
src/mainboard/Iwill/DK8S2/chip.h
View File

@ -1,4 +1,4 @@
extern struct chip_operations mainboard_Iwill_DK8S2_control;
extern struct chip_operations mainboard_Iwill_DK8S2_ops;
struct mainboard_Iwill_DK8S2_config {
int nothing;

4
src/mainboard/Iwill/DK8S2/cmos.layout
View File

@ -73,6 +73,4 @@ enumerations
checksums
checksum 392 1007 1008
checksum 392 983 984

9
src/mainboard/Iwill/DK8S2/mainboard.c
View File

@ -3,14 +3,9 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <arch/io.h>
#include "../../../northbridge/amd/amdk8/northbridge.h"
#include "chip.h"
struct chip_operations mainboard_Iwill_DK8S2_control = {
.enumerate = enumerate,
.name = "Iwill DK8S2 mainboard ",
struct chip_operations mainboard_Iwill_DK8S2_ops = {
CHIP_NAME("Iwill DK8S2 mainboard")
};

30
src/mainboard/Iwill/DK8S2/mptable.c
View File

@ -4,11 +4,11 @@
#include <string.h>
#include <stdint.h>
void *smp_write_config_table(void *v, unsigned long * processor_map)
void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "LNXI ";
static const char productid[12] = "HDAMA ";
static const char oem[8] = "IWILL ";
static const char productid[12] = "DK8X ";
struct mp_config_table *mc;
unsigned char bus_num;
unsigned char bus_isa;
@ -33,7 +33,7 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
mc->mpe_checksum = 0;
mc->reserved = 0;
smp_write_processors(mc, processor_map);
smp_write_processors(mc);
{
device_t dev;
@ -82,24 +82,25 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
smp_write_bus(mc, bus_isa, "ISA ");
/* IOAPIC handling */
smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
{
device_t dev;
uint32_t base;
struct resource *res;
/* 8131 apic 3 */
dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
if (dev) {
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
base &= PCI_BASE_ADDRESS_MEM_MASK;
smp_write_ioapic(mc, 0x03, 0x11, base);
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 0x03, 0x11, res->base);
}
}
/* 8131 apic 4 */
dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
if (dev) {
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
base &= PCI_BASE_ADDRESS_MEM_MASK;
smp_write_ioapic(mc, 0x04, 0x11, base);
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 0x04, 0x11, res->base);
}
}
}
@ -216,17 +217,16 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
/* Compute the checksums */
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk_debug("Wrote the mp table end at: %p - %p\n",
mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr);
return (unsigned long)smp_write_config_table(v, processor_map);
return (unsigned long)smp_write_config_table(v);
}

161
src/mainboard/Iwill/DK8X/Config.lb
View File

@ -1,110 +1,3 @@
uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
uses HARD_RESET_BUS
uses HARD_RESET_DEVICE
uses HARD_RESET_FUNCTION
uses IRQ_SLOT_COUNT
uses HAVE_OPTION_TABLE
uses CONFIG_MAX_CPUS
uses CONFIG_IOAPIC
uses CONFIG_SMP
uses FALLBACK_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_ROM_STREAM
uses CONFIG_ROM_STREAM_START
uses PAYLOAD_SIZE
uses _ROMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses STACK_SIZE
uses HEAP_SIZE
uses USE_OPTION_TABLE
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE=524288
###
### Build options
###
##
## Build code for the fallback boot
##
default HAVE_FALLBACK_BOOT=1
##
## Build code to reset the motherboard from linuxBIOS
##
default HAVE_HARD_RESET=1
default HARD_RESET_BUS=1
default HARD_RESET_DEVICE=4
default HARD_RESET_FUNCTION=0
##
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=9
##
## Build code to export an x86 MP table
## Useful for specifying IRQ routing values
##
default HAVE_MP_TABLE=1
##
## Build code to export a CMOS option table
##
default HAVE_OPTION_TABLE=1
##
## Build code for SMP support
## Only worry about 2 micro processors
##
default CONFIG_SMP=1
default CONFIG_MAX_CPUS=2
##
## Build code to setup a generic IOAPIC
##
default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
#default MAINBOARD_PART_NUMBER="HDAMA"
#default MAINBOARD_VENDOR="ARIMA"
###
### LinuxBIOS layout values
###
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
default ROM_IMAGE_SIZE = 65536
##
## Use a small 8K stack
##
default STACK_SIZE=0x2000
##
## Use a small 16K heap
##
default HEAP_SIZE=0x4000
##
## Only use the option table in a normal image
##
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
##
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
@ -123,7 +16,6 @@ end
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_STREAM = 1
##
## Compute where this copy of linuxBIOS will start in the boot rom
@ -145,15 +37,12 @@ default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
##
arch i386 end
#cpu k8 end
##
## Build the objects we have code for in this directory.
##
#object mainboard.o
driver mainboard.o
#object static_devices.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
@ -161,41 +50,41 @@ if HAVE_PIRQ_TABLE object irq_tables.o end
## Romcc output
##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
depends "./failover.E ./romcc"
action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "./auto.E ./romcc"
action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
##
mainboardinit cpu/i386/entry16.inc
mainboardinit cpu/i386/entry32.inc
ldscript /cpu/i386/entry16.lds
ldscript /cpu/i386/entry32.lds
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
##
## Build our reset vector (This is where linuxBIOS is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/i386/reset16.inc
ldscript /cpu/i386/reset16.lds
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
mainboardinit cpu/i386/reset32.inc
ldscript /cpu/i386/reset32.lds
mainboardinit cpu/x86/32bit/reset32.inc
ldscript /cpu/x86/32bit/reset32.lds
end
### Should this be in the northbridge code?
@ -207,11 +96,6 @@ mainboardinit arch/i386/lib/cpu_reset.inc
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
##
## Setup our mtrrs
##
mainboardinit cpu/k8/earlymtrr.inc
###
### This is the early phase of linuxBIOS startup
### Things are delicate and we test to see if we should
@ -229,9 +113,12 @@ end
##
## Setup RAM
##
mainboardinit cpu/k8/enable_mmx_sse.inc
mainboardinit cpu/x86/fpu/enable_fpu.inc
mainboardinit cpu/x86/mmx/enable_mmx.inc
mainboardinit cpu/x86/sse/enable_sse.inc
mainboardinit ./auto.inc
mainboardinit cpu/k8/disable_mmx_sse.inc
mainboardinit cpu/x86/sse/disable_sse.inc
mainboardinit cpu/x86/mmx/disable_mmx.inc
##
## Include the secondary Configuration files
@ -306,9 +193,3 @@ chip northbridge/amd/amdk8
end
end
##
## Include the old serial code for those few places that still need it.
##
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc

138
src/mainboard/Iwill/DK8X/auto.c
View File

@ -1,25 +1,51 @@
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <cpu/p6/apic.h>
#include <arch/io.h>
#include <device/pnp.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <arch/cpu.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#include "northbridge/amd/amdk8/early_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/k8/apic_timer.c"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#include "cpu/p6/boot_cpu.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
#include "superio/NSC/pc87360/pc87360_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#define SIO_BASE 0x2e
#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
static void hard_reset(void)
{
set_bios_reset();
/* enable cf9 */
pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
/* reset */
outb(0x0e, 0x0cf9);
}
static void soft_reset(void)
{
set_bios_reset();
pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
}
/*
* GPIO28 of 8111 will control H0_MEMRESET_L
* GPIO29 of 8111 will control H1_MEMRESET_L
*/
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
@ -103,68 +129,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "sdram/generic_sdram.c"
#include "northbridge/amd/amdk8/resourcemap.c"
static void enable_lapic(void)
{
msr_t msr;
msr = rdmsr(0x1b);
msr.hi &= 0xffffff00;
msr.lo &= 0x000007ff;
msr.lo |= APIC_DEFAULT_BASE | (1 << 11);
wrmsr(0x1b, msr);
}
static void stop_this_cpu(void)
{
unsigned apicid;
apicid = apic_read(APIC_ID) >> 24;
/* Send an APIC INIT to myself */
apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
/* Wait for the ipi send to finish */
apic_wait_icr_idle();
/* Deassert the APIC INIT */
apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
/* Wait for the ipi send to finish */
apic_wait_icr_idle();
/* If I haven't halted spin forever */
for(;;) {
hlt();
}
}
#define PC87360_FDC 0x00
#define PC87360_PP 0x01
#define PC87360_SP2 0x02
#define PC87360_SP1 0x03
#define PC87360_SWC 0x04
#define PC87360_KBCM 0x05
#define PC87360_KBCK 0x06
#define PC87360_GPIO 0x07
#define PC87360_ACB 0x08
#define PC87360_FSCM 0x09
#define PC87360_WDT 0x0A
static void pc87360_enable_serial(void)
{
pnp_set_logical_device(SIO_BASE, PC87360_SP1);
pnp_set_enable(SIO_BASE, 1);
pnp_set_iobase0(SIO_BASE, 0x3f8);
}
#define FIRST_CPU 1
#define SECOND_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
static void main(void)
static void main(unsigned long bist)
{
/*
* GPIO28 of 8111 will control H0_MEMRESET_L
* GPIO29 of 8111 will control H1_MEMRESET_L
*/
static const struct mem_controller cpu[] = {
#if FIRST_CPU
{
@ -189,22 +158,38 @@ static void main(void)
},
#endif
};
if (cpu_init_detected()) {
asm("jmp __cpu_reset");
int needs_reset;
if (bist == 0) {
/* Skip this if there was a built in self test failure */
amd_early_mtrr_init();
enable_lapic();
init_timer();
/* Has this cpu already booted? */
if (cpu_init_detected()) {
asm volatile ("jmp __cpu_reset");
}
distinguish_cpu_resets();
if (!boot_cpu()) {
stop_this_cpu();
}
}
enable_lapic();
init_timer();
if (!boot_cpu()) {
stop_this_cpu();
}
pc87360_enable_serial();
/* Setup the console */
pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
setup_default_resource_map();
setup_coherent_ht_domain();
enumerate_ht_chain(0);
distinguish_cpu_resets(0);
needs_reset = setup_coherent_ht_domain();
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
if (needs_reset) {
print_info("ht reset -\r\n");
soft_reset();
}
#if 0
print_pci_devices();
#endif
@ -212,6 +197,7 @@ static void main(void)
#if 0
dump_spd_registers(&cpu[0]);
#endif
memreset_setup();
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);

4
src/mainboard/Iwill/DK8X/chip.h
View File

@ -1,5 +1,5 @@
extern struct chip_operations mainboard_arima_hdama_control;
extern struct chip_operations mainboard_Iwill_DK8X_ops;
struct mainboard_arima_hdama_config {
struct mainboard_Iwill_DK8X_config {
int nothing;
};

29
src/mainboard/Iwill/DK8X/cmos.layout
View File

@ -29,6 +29,9 @@ entries
386 1 e 1 ECC_memory
388 4 r 0 reboot_bits
392 3 e 5 baud_rate
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
416 4 e 7 boot_first
@ -36,7 +39,15 @@ entries
424 4 e 7 boot_third
428 4 h 0 boot_index
432 8 h 0 boot_countdown
1008 16 h 0 check_sum
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory
enumerations
@ -66,9 +77,19 @@ enumerations
7 9 Fallback_HDD
7 10 Fallback_Floppy
#7 3 ROM
8 0 200Mhz
8 1 166Mhz
8 2 133Mhz
8 3 100Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
checksums
checksum 392 1007 1008
checksum 392 983 984

7
src/mainboard/Iwill/DK8X/mainboard.c
View File

@ -3,12 +3,9 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <arch/io.h>
#include "../../../northbridge/amd/amdk8/northbridge.h"
#include "chip.h"
struct chip_operations mainboard_arima_hdama_control = {
.name = "Arima HDAMA mainboard ",
struct chip_operations mainboard_Iwill_DK8X_ops = {
CHIP_NAME("Iwill DK8X mainboard")
};

30
src/mainboard/Iwill/DK8X/mptable.c
View File

@ -4,11 +4,11 @@
#include <string.h>
#include <stdint.h>
void *smp_write_config_table(void *v, unsigned long * processor_map)
void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "LNXI ";
static const char productid[12] = "HDAMA ";
static const char oem[8] = "IWILL ";
static const char productid[12] = "DK8X ";
struct mp_config_table *mc;
unsigned char bus_num;
unsigned char bus_isa;
@ -33,7 +33,7 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
mc->mpe_checksum = 0;
mc->reserved = 0;
smp_write_processors(mc, processor_map);
smp_write_processors(mc);
{
device_t dev;
@ -82,24 +82,25 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
smp_write_bus(mc, bus_isa, "ISA ");
/* IOAPIC handling */
smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
{
device_t dev;
uint32_t base;
struct resource *res;
/* 8131 apic 3 */
dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
if (dev) {
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
base &= PCI_BASE_ADDRESS_MEM_MASK;
smp_write_ioapic(mc, 0x03, 0x11, base);
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 0x03, 0x11, res->base);
}
}
/* 8131 apic 4 */
dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
if (dev) {
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
base &= PCI_BASE_ADDRESS_MEM_MASK;
smp_write_ioapic(mc, 0x04, 0x11, base);
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 0x04, 0x11, res->base);
}
}
}
@ -216,17 +217,16 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
/* Compute the checksums */
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk_debug("Wrote the mp table end at: %p - %p\n",
mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr);
return (unsigned long)smp_write_config_table(v, processor_map);
return (unsigned long)smp_write_config_table(v);
}

16
src/mainboard/amd/quartet/Config.lb
View File

@ -46,22 +46,22 @@ if HAVE_PIRQ_TABLE object irq_tables.o end
## Romcc output
##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
depends "./failover.E ./romcc"
action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c option_table.h"
action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "./auto.E ./romcc"
action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
##

51
src/mainboard/amd/quartet/auto.c
View File

@ -7,7 +7,8 @@
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/smp/lapic.h>
#include <cpu/x86/lapic.h>
#include <arch/cpu.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
@ -16,13 +17,15 @@
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/k8/apic_timer.c"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#include "cpu/p6/boot_cpu.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
#include "superio/NSC/pc87360/pc87360_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
@ -41,7 +44,10 @@ static void soft_reset(void)
pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
}
/*
* GPIO28 of 8111 will control H0_MEMRESET_L
* GPIO29 of 8111 will control H1_MEMRESET_L
*/
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
@ -144,13 +150,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "fakespd.c"
#endif
#include "northbridge/amd/amdk8/setup_resource_map.c"
// #include "northbridge/amd/amdk8/setup_resource_map.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
#include "resourcemap.c" /* quartet does not want the default */
#define RC0 ((1<<1)<<8)
@ -163,7 +166,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#define DIMM2 0x52
#define DIMM3 0x53
static void main(void)
static void main(unsigned long bist)
{
static const struct mem_controller cpu[] = {
{
@ -215,22 +218,30 @@ static void main(void)
int needs_reset;
enable_lapic();
init_timer();
if (bist == 0) {
/* Skip this if there was a built in self test failure */
amd_early_mtrr_init();
enable_lapic();
init_timer();
/* Has this cpu already booted? */
if (cpu_init_detected()) {
asm volatile ("jmp __cpu_reset");
}
if (cpu_init_detected()) {
asm("jmp __cpu_reset");
distinguish_cpu_resets();
if (!boot_cpu()) {
stop_this_cpu();
}
}
distinguish_cpu_resets();
if (!boot_cpu()) {
stop_this_cpu();
}
/* Setup the console */
pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
setup_quartet_resource_map();
needs_reset = setup_coherent_ht_domain();
// needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);

2
src/mainboard/amd/quartet/chip.h
View File

@ -1,4 +1,4 @@
extern struct chip_operations mainboard_amd_quartet_control;
extern struct chip_operations mainboard_amd_quartet_ops;
struct mainboard_amd_quartet_config {
int nothing;

7
src/mainboard/amd/quartet/mainboard.c
View File

@ -3,12 +3,9 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <arch/io.h>
#include "../../../northbridge/amd/amdk8/northbridge.h"
#include "chip.h"
struct chip_operations mainboard_amd_quartet_control = {
.name = "AMD Quartet mainboard ",
struct chip_operations mainboard_amd_quartet_ops = {
CHIP_NAME("AMD Quartet mainboard ")
};

26
src/mainboard/amd/quartet/mptable.c
View File

@ -4,7 +4,7 @@
#include <string.h>
#include <stdint.h>
void *smp_write_config_table(void *v, unsigned long * processor_map)
void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "AMD ";
@ -33,7 +33,7 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
mc->mpe_checksum = 0;
mc->reserved = 0;
smp_write_processors(mc, processor_map);
smp_write_processors(mc);
{
device_t dev;
@ -82,24 +82,25 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
smp_write_bus(mc, bus_isa, "ISA ");
/* IOAPIC handling */
smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
{
device_t dev;
uint32_t base;
struct resource *res;
/* 8131 apic 3 */
dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
if (dev) {
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
base &= PCI_BASE_ADDRESS_MEM_MASK;
smp_write_ioapic(mc, 0x03, 0x11, base);
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 0x03, 0x11, res->base);
}
}
/* 8131 apic 4 */
dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
if (dev) {
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
base &= PCI_BASE_ADDRESS_MEM_MASK;
smp_write_ioapic(mc, 0x04, 0x11, base);
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 0x04, 0x11, res->base);
}
}
}
@ -216,17 +217,16 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
/* Compute the checksums */
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk_debug("Wrote the mp table end at: %p - %p\n",
mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr);
return (unsigned long)smp_write_config_table(v, processor_map);
return (unsigned long)smp_write_config_table(v);
}

24
src/mainboard/amd/serenade/Config.lb
View File

@ -46,22 +46,22 @@ if HAVE_PIRQ_TABLE object irq_tables.o end
## Romcc output
##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
depends "./failover.E ./romcc"
action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c option_table.h"
action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "./auto.E ./romcc"
action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
##
@ -76,11 +76,11 @@ ldscript /cpu/x86/32bit/entry32.lds
## Build our reset vector (This is where linuxBIOS is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
mainboardinit cpu/x86/32bit/reset32.inc
ldscript /cpu/x86/32bit/reset32.lds
mainboardinit cpu/x86/32bit/reset32.inc
ldscript /cpu/x86/32bit/reset32.lds
end
### Should this be in the northbridge code?

48
src/mainboard/amd/serenade/auto.c
View File

@ -6,7 +6,8 @@
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/smp/lapic.h>
#include <cpu/x86/lapic.h>
#include <arch/cpu.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
@ -15,13 +16,15 @@
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/k8/apic_timer.c"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#include "cpu/p6/boot_cpu.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@ -41,6 +44,10 @@ static void soft_reset(void)
pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
}
/*
* GPIO16 of 8111 will control H0_MEMRESET_L
* GPIO17 of 8111 will control H1_MEMRESET_L
*/
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
@ -126,12 +133,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#define FIRST_CPU 1
#define SECOND_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
static void main(void)
static void main(unsigned long bist)
{
/*
* GPIO28 of 8111 will control H0_MEMRESET_L
* GPIO29 of 8111 will control H1_MEMRESET_L
*/
static const struct mem_controller cpu[] = {
#if FIRST_CPU
{
@ -156,24 +159,31 @@ static void main(void)
},
#endif
};
int needs_reset;
if (bist == 0) {
/* Skip this if there was a built in self test failure */
amd_early_mtrr_init();
enable_lapic();
init_timer();
/* Has this cpu already booted? */
if (cpu_init_detected()) {
asm volatile ("jmp __cpu_reset");
}
enable_lapic();
init_timer();
if (cpu_init_detected()) {
asm("jmp __cpu_reset");
distinguish_cpu_resets();
if (!boot_cpu()) {
stop_this_cpu();
}
}
distinguish_cpu_resets();
if (!boot_cpu()) {
stop_this_cpu();
}
/* Setup the console */
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
#if 0
print_pci_devices();
#endif

2
src/mainboard/amd/serenade/chip.h
View File

@ -1,4 +1,4 @@
extern struct chip_operations mainboard_amd_serenade_control;
extern struct chip_operations mainboard_amd_serenade_ops;
struct mainboard_amd_serenade_config {
int nothing;

7
src/mainboard/amd/serenade/mainboard.c
View File

@ -3,11 +3,8 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <arch/io.h>
#include "../../../northbridge/amd/amdk8/northbridge.h"
#include "chip.h"
struct chip_operations mainboard_amd_serenade_control = {
.name = "AMD Serenade mainboard ",
struct chip_operations mainboard_amd_serenade_ops = {
CHIP_NAME("AMD Serenade mainboard ")
};

24
src/mainboard/amd/serenade/mptable.c
View File

@ -4,7 +4,7 @@
#include <string.h>
#include <stdint.h>
void *smp_write_config_table(void *v, unsigned long * processor_map)
void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "AMD ";
@ -35,7 +35,7 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
mc->mpe_checksum = 0;
mc->reserved = 0;
smp_write_processors(mc, processor_map);
smp_write_processors(mc);
{
device_t dev;
@ -83,20 +83,22 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
{
device_t dev;
uint32_t base;
struct resource *res;
/* 8131-1 apic #3 */
dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
if (dev) {
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
base &= PCI_BASE_ADDRESS_MEM_MASK;
smp_write_ioapic(mc, 0x03, 0x11, base);
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 0x03, 0x11, res->base);
}
}
/* 8131-2 apic #4 */
dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
if (dev) {
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
base &= PCI_BASE_ADDRESS_MEM_MASK;
smp_write_ioapic(mc, 0x04, 0x11, base);
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 0x04, 0x11, res->base);
}
}
}
@ -164,10 +166,10 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
return smp_next_mpe_entry(mc);
}
unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr);
return (unsigned long)smp_write_config_table(v, processor_map);
return (unsigned long)smp_write_config_table(v);
}

16
src/mainboard/amd/solo/Config.lb
View File

@ -47,22 +47,22 @@ if HAVE_PIRQ_TABLE object irq_tables.o end
## Romcc output
##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
depends "./failover.E ./romcc"
action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c option_table.h "
action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "./auto.E ./romcc"
action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
##

24
src/mainboard/amd/solo/mainboard.c
View File

@ -4,30 +4,8 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <arch/io.h>
#include "../../../northbridge/amd/amdk8/northbridge.h"
#include "chip.h"
static void mainboard_init(device_t dev)
{
root_dev_init(dev);
}
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = root_dev_enable_resources,
.init = mainboard_init,
.scan_bus = root_dev_scan_bus,
.enable = 0,
};
static void enable_dev(struct device *dev)
{
dev->ops = &mainboard_operations;
}
struct chip_operations mainboard_amd_solo_ops = {
.enable_dev = enable_dev,
CHIP_NAME("AMD Solo7 mainboard")
};

14
src/mainboard/arima/hdama/Config.lb
View File

@ -32,7 +32,11 @@ default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default XIP_ROM_SIZE=65536
default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
arch i386 end
##
## Set all of the defaults for an x86 architecture
##
arch i386 end
##
## Build the objects we have code for in this directory.
@ -77,11 +81,11 @@ ldscript /cpu/x86/32bit/entry32.lds
## Build our reset vector (This is where linuxBIOS is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
mainboardinit cpu/x86/32bit/reset32.inc
ldscript /cpu/x86/32bit/reset32.lds
mainboardinit cpu/x86/32bit/reset32.inc
ldscript /cpu/x86/32bit/reset32.lds
end
### Should this be in the northbridge code?

2
src/mainboard/arima/hdama/cmos.layout
View File

@ -93,5 +93,3 @@ enumerations
checksums
checksum 392 983 984

307
src/mainboard/arima/hdama/mainboard.c
View File

@ -7,315 +7,10 @@
#include <part/hard_reset.h>
#include <device/smbus.h>
#include <delay.h>
#include <arch/io.h>
#include "../../../northbridge/amd/amdk8/northbridge.h"
#include "../../../northbridge/amd/amdk8/cpu_rev.c"
#include "chip.h"
#include "pc80/mc146818rtc.h"
#undef DEBUG
#define DEBUG 0
#if DEBUG
static void debug_init(device_t dev)
{
unsigned bus;
unsigned devfn;
#if 0
for(bus = 0; bus < 256; bus++) {
for(devfn = 0; devfn < 256; devfn++) {
int i;
dev = dev_find_slot(bus, devfn);
if (!dev) {
continue;
}
if (!dev->enabled) {
continue;
}
printk_info("%02x:%02x.%0x aka %s\n",
bus, devfn >> 3, devfn & 7, dev_path(dev));
for(i = 0; i < 256; i++) {
if ((i & 0x0f) == 0) {
printk_info("%02x:", i);
}
printk_info(" %02x", pci_read_config8(dev, i));
if ((i & 0x0f) == 0xf) {
printk_info("\n");
}
}
printk_info("\n");
}
}
#endif
#if 0
msr_t msr;
unsigned index;
unsigned eax, ebx, ecx, edx;
index = 0x80000007;
printk_debug("calling cpuid 0x%08x\n", index);
asm volatile(
"cpuid"
: "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
: "a" (index)
);
printk_debug("cpuid[%08x]: %08x %08x %08x %08x\n",
index, eax, ebx, ecx, edx);
if (edx & (3 << 1)) {
index = 0xC0010042;
printk_debug("Reading msr: 0x%08x\n", index);
msr = rdmsr(index);
printk_debug("msr[0x%08x]: 0x%08x%08x\n",
index, msr.hi, msr.hi);
}
#endif
}
static void debug_noop(device_t dummy)
{
}
static struct device_operations debug_operations = {
.read_resources = debug_noop,
.set_resources = debug_noop,
.enable_resources = debug_noop,
.init = debug_init,
};
static unsigned int scan_root_bus(device_t root, unsigned int max)
{
struct device_path path;
device_t debug;
max = root_dev_scan_bus(root, max);
path.type = DEVICE_PATH_PNP;
path.u.pnp.port = 0;
path.u.pnp.device = 0;
debug = alloc_dev(&root->link[1], &path);
debug->ops = &debug_operations;
return max;
}
#endif
#if 0
static void handle_smbus_error(int value, const char *msg)
{
if (value >= 0) {
return;
}
switch(value) {
case SMBUS_WAIT_UNTIL_READY_TIMEOUT:
printk_emerg("SMBUS wait until ready timed out - resetting...");
hard_reset();
break;
case SMBUS_WAIT_UNTIL_DONE_TIMEOUT:
printk_emerg("SMBUS wait until done timed out - resetting...");
hard_reset();
break;
default:
die(msg);
break;
}
}
#define ADM1026_DEVICE 0x2c /* 0x2e or 0x2d */
#define ADM1026_REG_CONFIG1 0x00
#define CFG1_MONITOR 0x01
#define CFG1_INT_ENABLE 0x02
#define CFG1_INT_CLEAR 0x04
#define CFG1_AIN8_9 0x08
#define CFG1_THERM_HOT 0x10
#define CFT1_DAC_AFC 0x20
#define CFG1_PWM_AFC 0x40
#define CFG1_RESET 0x80
#define ADM1026_REG_CONFIG2 0x01
#define ADM1026_REG_CONFIG3 0x07
#define BILLION 1000000000UL
static void verify_cpu_voltage(const char *name,
device_t dev, unsigned int reg,
unsigned factor, unsigned cpu_volts, unsigned delta)
{
unsigned nvolts_lo, nvolts_hi;
unsigned cpuvolts_hi, cpuvolts_lo;
int value;
int loops;
loops = 1000;
do {
value = smbus_read_byte(dev, reg);
handle_smbus_error(value, "SMBUS read byte failed");
} while ((--loops > 0) && value == 0);
/* Convert the byte value to nanoVolts.
* My accuracy is nowhere near that good but I don't
* have to round so the math is simple.
* I can only go up to about 4.2 Volts this way so my range is
* limited.
*/
nvolts_lo = ((unsigned)value * factor);
nvolts_hi = nvolts_lo + factor - 1;
/* Get the range of acceptable cpu voltage values */
cpuvolts_lo = cpu_volts - delta;
cpuvolts_hi = cpu_volts + delta;
if ((nvolts_lo < cpuvolts_lo) || (nvolts_hi > cpuvolts_hi)) {
printk_emerg("%s at (%u.%09u-%u.%09u)Volts expected %u.%09u+/-%u.%09uVolts\n",
name,
nvolts_lo/BILLION, nvolts_lo%BILLION,
nvolts_hi/BILLION, nvolts_hi%BILLION,
cpu_volts/BILLION, cpu_volts%BILLION,
delta/BILLION, delta%BILLION);
die("");
}
printk_info("%s at (%u.%09u-%u.%09u)Volts\n",
name,
nvolts_lo/BILLION, nvolts_lo%BILLION,
nvolts_hi/BILLION, nvolts_hi%BILLION);
}
static void adm1026_enable_monitoring(device_t dev)
{
int result;
result = smbus_read_byte(dev, ADM1026_REG_CONFIG1);
handle_smbus_error(result, "ADM1026: cannot read config1");
result = (result | CFG1_MONITOR) & ~(CFG1_INT_CLEAR | CFG1_RESET);
result = smbus_write_byte(dev, ADM1026_REG_CONFIG1, result);
handle_smbus_error(result, "ADM1026: cannot write to config1");
result = smbus_read_byte(dev, ADM1026_REG_CONFIG1);
handle_smbus_error(result, "ADM1026: cannot reread config1");
if (!(result & CFG1_MONITOR)) {
die("ADM1026: monitoring would not enable");
}
}
static unsigned k8_cpu_volts(void)
{
unsigned volts = ~0;
if (is_cpu_c0()) {
volts = 1500000000;
}
if (is_cpu_b3()) {
volts = 1550000000;
}
return volts;
}
static void verify_cpu_voltages(device_t dev)
{
unsigned cpu_volts;
unsigned delta;
#if 0
delta = 50000000;
#else
delta = 75000000;
#endif
cpu_volts = k8_cpu_volts();
if (cpu_volts == ~0) {
printk_info("Required cpu voltage unknwon not checking\n");
return;
}
/* I need to read registers 0x37 == Ain7CPU1 core 0x2d == VcppCPU0 core */
/* CPU1 core
* The sensor has a range of 0-2.5V and reports in
* 256 distinct steps.
*/
verify_cpu_voltage("CPU1 Vcore", dev, 0x37, 9765625,
cpu_volts, delta);
/* CPU0 core
* The sensor has range of 0-3.0V and reports in
* 256 distinct steps.
*/
verify_cpu_voltage("CPU0 Vcore", dev, 0x2d, 11718750,
cpu_volts, delta);
}
#define SMBUS_MUX 0x70
static void do_verify_cpu_voltages(void)
{
device_t smbus_dev;
device_t mux, sensor;
struct device_path mux_path, sensor_path;
int result;
int mux_setting;
/* Find the smbus controller */
smbus_dev = dev_find_device(0x1022, 0x746b, 0);
if (!smbus_dev) {
die("SMBUS controller not found\n");
}
/* Find the smbus mux */
mux_path.type = DEVICE_PATH_I2C;
mux_path.u.i2c.device = SMBUS_MUX;
mux = find_dev_path(smbus_dev, &mux_path);
if (!mux) {
die("SMBUS mux not found\n");
}
/* Find the adm1026 sensor */
sensor_path.type = DEVICE_PATH_I2C;
sensor_path.u.i2c.device = ADM1026_DEVICE;
sensor = find_dev_path(mux, &sensor_path);
if (!sensor) {
die("ADM1026 not found\n");
}
/* Set the mux to see the temperature sensors */
mux_setting = 1;
result = smbus_send_byte(mux, mux_setting);
handle_smbus_error(result, "SMBUS send byte failed\n");
result = smbus_recv_byte(mux);
handle_smbus_error(result, "SMBUS recv byte failed\n");
if (result != mux_setting) {
printk_emerg("SMBUS mux would not set to %d\n", mux_setting);
die("");
}
adm1026_enable_monitoring(sensor);
/* It takes 11.38ms to read a new voltage sensor value */
mdelay(12);
/* Read the cpu voltages and make certain everything looks sane */
verify_cpu_voltages(sensor);
}
#else
#define do_verify_cpu_voltages() do {} while(0)
#endif
static void mainboard_init(device_t dev)
{
root_dev_init(dev);
do_verify_cpu_voltages();
}
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = root_dev_enable_resources,
.init = mainboard_init,
#if !DEBUG
.scan_bus = root_dev_scan_bus,
#else
.scan_bus = scan_root_bus,
#endif
.enable = 0,
};
static void enable_dev(struct device *dev)
{
dev->ops = &mainboard_operations;
}
struct chip_operations mainboard_arima_hdama_ops = {
.enable_dev = enable_dev,
CHIP_NAME("Arima Hdama mainboard")
};

172
src/mainboard/densitron/dpx114/Config.lb
View File

@ -1,86 +1,3 @@
uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
uses HAVE_OPTION_TABLE
uses USE_OPTION_TABLE
uses CONFIG_ROM_STREAM
uses IRQ_SLOT_COUNT
uses MAINBOARD
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
uses HEAP_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_ROM_STREAM_START
uses PAYLOAD_SIZE
uses _ROMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses HAVE_MP_TABLE
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256*1024
###
### Build options
###
##
## Build code for the fallback boot
##
default HAVE_FALLBACK_BOOT=1
##
## no MP table
##
default HAVE_MP_TABLE=0
##
## Build code to reset the motherboard from linuxBIOS
##
default HAVE_HARD_RESET=1
##
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=5
object irq_tables.o
##
## Build code to export a CMOS option table
##
default HAVE_OPTION_TABLE=1
###
### LinuxBIOS layout values
###
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
default ROM_IMAGE_SIZE = 65536
##
## Use a small 8K stack
##
default STACK_SIZE=0x2000
##
## Use a small 16K heap
##
default HEAP_SIZE=0x4000
##
## Only use the option table in a normal image
##
#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
default USE_OPTION_TABLE = 0
##
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
@ -99,7 +16,6 @@ end
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_STREAM = 1
##
## Compute where this copy of linuxBIOS will start in the boot rom
@ -126,49 +42,49 @@ arch i386 end
## Build the objects we have code for in this directory.
##
driver mainboard.o
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
##
## Romcc output
##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
depends "./failover.E ./romcc"
action "./romcc -O -mcpu=c3 -o failover.inc --label-prefix=failover ./failover.E"
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "./auto.E ./romcc"
action "./romcc -O -mcpu=c3 ./auto.E "
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
##
mainboardinit cpu/i386/entry16.inc
mainboardinit cpu/i386/entry32.inc
ldscript /cpu/i386/entry16.lds
ldscript /cpu/i386/entry32.lds
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
##
## Build our reset vector (This is where linuxBIOS is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/i386/reset16.inc
ldscript /cpu/i386/reset16.lds
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
mainboardinit cpu/i386/reset32.inc
ldscript /cpu/i386/reset32.lds
mainboardinit cpu/x86/32bit/reset32.inc
ldscript /cpu/x86/32bit/reset32.lds
end
### Should this be in the northbridge code?
@ -180,11 +96,6 @@ mainboardinit arch/i386/lib/cpu_reset.inc
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
##
## Setup our mtrrs
##
# mainboardinit cpu/p6/earlymtrr.inc
###
### This is the early phase of linuxBIOS startup
### Things are delicate and we test to see if we should
@ -202,7 +113,10 @@ end
##
## Setup RAM
##
mainboardinit cpu/x86/fpu/enable_fpu.inc
mainboardinit cpu/x86/mmx/enable_mmx.inc
mainboardinit ./auto.inc
mainboardinit cpu/x86/mmx/disable_mmx.inc
##
## Include the secondary Configuration files
@ -210,32 +124,24 @@ mainboardinit ./auto.inc
dir /pc80
config chip.h
northbridge via/vt8601 "vt8601"
# pci 0:0.0
# pci 0:1.0
southbridge via/vt8231 "vt8231"
# pci 0:11.0
# pci 0:11.1
# pci 0:11.2
# pci 0:11.3
# pci 0:11.4
# pci 0:11.5
# pci 0:11.6
# pci 0:12.0
register "enable_usb" = "0"
register "enable_native_ide" = "0"
register "enable_com_ports" = "1"
register "enable_keyboard" = "0"
register "enable_nvram" = "1"
chip northbridge/via/vt8601
device pci_domain 0 on
chip southbridge/via/vt8231
register "enable_usb" = "0"
register "enable_native_ide" = "0"
register "enable_com_ports" = "1"
register "enable_keyboard" = "0"
register "enable_nvram" = "1"
# device pci 0:11.0 on end
# device pci 0:11.1 on end
# device pci 0:11.2 on end
# device pci 0:11.3 on end
# device pci 0:11.4 on end
# device pci 0:11.5 on end
# device pci 0:11.6 on end
# device pci 0:12.0 on end
end
end
chip cpu/via/model_centaur
end
end
cpu p6 "cpu0"
end
##
## Include the old serial code for those few places that still need it.
##
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc

38
src/mainboard/densitron/dpx114/auto.c
View File

@ -2,7 +2,9 @@
#include <stdint.h>
#include <device/pci_def.h>
#include <cpu/p6/apic.h>
#if 0
#include <cpu/x86/lapic.h>
#endif
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
@ -11,7 +13,8 @@
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#include "northbridge/via/vt8601/raminit.h"
#include "cpu/p6/earlymtrr.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
/*
*/
@ -23,10 +26,22 @@ void udelay(int usecs)
}
#include "lib/delay.c"
#include "cpu/p6/boot_cpu.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "debug.c"
#include "southbridge/via/vt8231/vt8231_early_smbus.c"
#include "southbridge/via/vt8231/vt8231_early_serial.c"
static inline int spd_read_byte(unsigned device, unsigned address)
{
unsigned char c;
c = smbus_read_byte(device, address);
return c;
}
#include "northbridge/via/vt8601/raminit.c"
static void enable_mainboard_devices(void)
{
@ -68,16 +83,22 @@ static void enable_shadow_ram(void)
pci_write_config8(dev, 0x63, shadowreg);
}
static void main(void)
static void main(unsigned long bist)
{
unsigned long x;
/* init_timer();*/
outb(5, 0x80);
enable_vt8231_serial();
if (bist == 0) {
early_mtrr_init();
}
enable_vt8231_serial();
uart_init();
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
/* init_timer();*/
outb(5, 0x80);
enable_mainboard_devices();
enable_smbus();
@ -102,5 +123,4 @@ static void main(void)
ram_check(check_addrs[i].lo, check_addrs[i].hi);
}
#endif
early_mtrr_init();
}

2
src/mainboard/densitron/dpx114/chip.h
View File

@ -1,4 +1,4 @@
extern struct chip_operations mainboard_densitron_dpx114_control;
extern struct chip_operations mainboard_densitron_dpx114_ops;
struct mainboard_densitron_dpx114_config {
int nothing;

37
src/mainboard/densitron/dpx114/failover.c
View File

@ -5,25 +5,28 @@
#include <arch/io.h>
#include "arch/romcc_io.h"
#include "pc80/mc146818rtc_early.c"
#include "cpu/p6/boot_cpu.c"
static void main(void)
static unsigned long main(unsigned long bist)
{
/* for now, just always assume failure */
#if 0
/* Is this a cpu reset? */
if (cpu_init_detected()) {
if (last_boot_normal()) {
asm("jmp __normal_image");
} else {
asm("jmp __cpu_reset");
}
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
asm("jmp __normal_image");
if (do_normal_boot()) {
goto normal_image;
}
#endif
else {
goto fallback_image;
}
normal_image:
asm volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
: /* clobbers */
);
cpu_reset:
asm volatile ("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
: /* clobbers */
);
fallback_image:
return bist;
}

30
src/mainboard/densitron/dpx114/mainboard.c
View File

@ -3,35 +3,9 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <arch/io.h>
#include "chip.h"
static int
mainboard_scan_bus(device_t root, int maxbus)
{
int retval;
printk_spew("%s: root %p maxbus %d\n", __FUNCTION__, root, maxbus);
retval = pci_scan_bus(root->bus, 0, 0xff, maxbus);
printk_spew("DONE %s: return %d\n", __FUNCTION__, maxbus);
return maxbus;
}
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = root_dev_enable_resources,
.init = root_dev_init,
.scan_bus = mainboard_scan_bus,
.enable = 0,
};
static void enable_dev(device_t dev)
{
dev->ops = &mainboard_operations;
}
struct chip_operations mainboard_via_epia_control = {
.enable_dev = enable_dev,
.name = "VIA EPIA mainboard ",
struct chip_operations mainboard_densitron_dpx114_ops = {
CHIP_NAME("Densitron DPX114 mainboard ")
};

129
src/mainboard/digitallogic/adl855pc/Config.lb
View File

@ -1,86 +1,3 @@
uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
uses HAVE_OPTION_TABLE
uses USE_OPTION_TABLE
uses CONFIG_ROM_STREAM
uses IRQ_SLOT_COUNT
uses MAINBOARD
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
uses HEAP_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_ROM_STREAM_START
uses PAYLOAD_SIZE
uses _ROMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses HAVE_MP_TABLE
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256*1024
###
### Build options
###
##
## Build code for the fallback boot
##
default HAVE_FALLBACK_BOOT=1
##
## no MP table
##
default HAVE_MP_TABLE=0
##
## Build code to reset the motherboard from linuxBIOS
##
default HAVE_HARD_RESET=1
##
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=5
object irq_tables.o
##
## Build code to export a CMOS option table
##
default HAVE_OPTION_TABLE=1
###
### LinuxBIOS layout values
###
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
default ROM_IMAGE_SIZE = 65536
##
## Use a small 8K stack
##
default STACK_SIZE=0x2000
##
## Use a small 16K heap
##
default HEAP_SIZE=0x4000
##
## Only use the option table in a normal image
##
#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
default USE_OPTION_TABLE = 0
##
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
@ -99,7 +16,6 @@ end
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_STREAM = 1
##
## Compute where this copy of linuxBIOS will start in the boot rom
@ -126,49 +42,49 @@ arch i386 end
## Build the objects we have code for in this directory.
##
driver mainboard.o
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
##
## Romcc output
##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
depends "./failover.E ./romcc"
action "./romcc -O -mcpu=p4 -o failover.inc --label-prefix=failover ./failover.E"
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "./auto.E ./romcc"
action "./romcc -O -mcpu=p4 ./auto.E "
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
##
mainboardinit cpu/i386/entry16.inc
mainboardinit cpu/i386/entry32.inc
ldscript /cpu/i386/entry16.lds
ldscript /cpu/i386/entry32.lds
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
##
## Build our reset vector (This is where linuxBIOS is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/i386/reset16.inc
ldscript /cpu/i386/reset16.lds
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
mainboardinit cpu/i386/reset32.inc
ldscript /cpu/i386/reset32.lds
mainboardinit cpu/x86/32bit/reset32.inc
ldscript /cpu/x86/32bit/reset32.lds
end
### Should this be in the northbridge code?
@ -180,11 +96,6 @@ mainboardinit arch/i386/lib/cpu_reset.inc
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
##
## Setup our mtrrs
##
# mainboardinit cpu/p6/earlymtrr.inc
###
### This is the early phase of linuxBIOS startup
### Things are delicate and we test to see if we should
@ -203,7 +114,7 @@ end
## Setup RAM
##
mainboardinit cpu/x86/fpu/enable_fpu.inc
mainboardinit cpu/x86/mmx/emable_mmx.inc
mainboardinit cpu/x86/mmx/enable_mmx.inc
mainboardinit cpu/x86/sse/enable_sse.inc
mainboardinit ./auto.inc
mainboardinit cpu/x86/sse/disable_sse.inc
@ -273,8 +184,8 @@ chip northbridge/intel/i855pm
end
end
device apic_cluster 0 on
device cpu/intel/socket_mPGA479M
apic 0
chip cpu/intel/socket_mPGA479M
device apic 0 on end
end
end
end

25
src/mainboard/digitallogic/adl855pc/auto.c
View File

@ -5,7 +5,10 @@
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#if 0
#include <arch/smp/lapic.h>
#endif
#include <arch/hlt.h>
//#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
@ -14,16 +17,16 @@
#include "southbridge/intel/i82801dbm/i82801dbm_early_smbus.c"
#include "northbridge/intel/i855pm/raminit.h"
#if 1
#if 0
#include "cpu/p6/apic_timer.c"
#include "lib/delay.c"
#endif
#include "cpu/p6/boot_cpu.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/intel/i855pm/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/p6/earlymtrr.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@ -57,7 +60,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/intel/i855pm/reset_test.c"
#include "sdram/generic_sdram.c"
static void main(void)
static void main(unsigned long bist)
{
static const struct mem_controller memctrl[] = {
{
@ -66,15 +69,21 @@ static void main(void)
},
};
#if 1
enable_lapic();
init_timer();
if (bist == 0) {
early_mtrr_init();
#if 0
enable_lapic();
init_timer();
#endif
}
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
#if 0
print_pci_devices();
#endif

2
src/mainboard/digitallogic/adl855pc/chip.h
View File

@ -1,4 +1,4 @@
extern struct chip_operations mainboard_digitallogic_adl855pc_control;
extern struct chip_operations mainboard_digitallogic_adl855pc_ops;
struct mainboard_digitallogic_adl855pc_config {
int nothing;

37
src/mainboard/digitallogic/adl855pc/failover.c
View File

@ -5,25 +5,28 @@
#include <arch/io.h>
#include "arch/romcc_io.h"
#include "pc80/mc146818rtc_early.c"
#include "cpu/p6/boot_cpu.c"
static void main(void)
static unsigned long main(unsigned long bist)
{
/* for now, just always assume failure */
#if 0
/* Is this a cpu reset? */
if (cpu_init_detected()) {
if (last_boot_normal()) {
asm("jmp __normal_image");
} else {
asm("jmp __cpu_reset");
}
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
asm("jmp __normal_image");
if (do_normal_boot()) {
goto normal_image;
}
#endif
else {
goto fallback_image;
}
normal_image:
asm volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
: /* clobbers */
);
cpu_reset:
asm volatile ("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
: /* clobbers */
);
fallback_image:
return bist;
}

30
src/mainboard/digitallogic/adl855pc/mainboard.c
View File

@ -3,35 +3,9 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <arch/io.h>
#include "chip.h"
static int
mainboard_scan_bus(device_t root, int maxbus)
{
int retval;
printk_spew("%s: root %p maxbus %d\n", __FUNCTION__, root, maxbus);
retval = pci_scan_bus(root->bus, 0, 0xff, maxbus);
printk_spew("DONE %s: return %d\n", __FUNCTION__, maxbus);
return maxbus;
}
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = root_dev_enable_resources,
.init = root_dev_init,
.scan_bus = mainboard_scan_bus,
.enable = 0,
};
static void enable_dev(device_t dev)
{
dev->ops = &mainboard_operations;
}
struct chip_operations mainboard_digitallogic_adl855pc_control = {
.enable_dev = enable_dev,
.name = "Digital Logic ADL855PC mainboard ",
struct chip_operations mainboard_digitallogic_adl855pc_ops = {
CHIP_NAME("Digital Logic ADL855PC mainboard ")
};

2
src/mainboard/emulation/qemu-i386/auto.c
View File

@ -7,6 +7,8 @@
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"

27
src/mainboard/emulation/qemu-i386/mainboard.c
View File

@ -3,34 +3,9 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <arch/io.h>
#include "chip.h"
static int mainboard_scan_bus(device_t root, int maxbus)
{
int retval;
printk_spew("%s: root %p maxbus %d\n", __FUNCTION__, root, maxbus);
retval = pci_scan_bus(root->bus, 0, 0xff, maxbus);
printk_spew("DONE %s: return %d\n", __FUNCTION__, maxbus);
return maxbus;
}
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = root_dev_enable_resources,
.init = root_dev_init,
.scan_bus = mainboard_scan_bus,
};
static void enable_dev(struct device *dev)
{
dev->ops = &mainboard_operations;
}
struct chip_operations mainboard_emulation_qemu_i386_ops = {
.enable_dev = enable_dev,
//.name = "qemu mainboard ",
CHIP_NAME("qemu mainboard ")
};

174
src/mainboard/ibm/e325/Config.lb
View File

@ -1,123 +1,3 @@
uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
uses HARD_RESET_BUS
uses HARD_RESET_DEVICE
uses HARD_RESET_FUNCTION
uses IRQ_SLOT_COUNT
uses HAVE_OPTION_TABLE
uses CONFIG_MAX_CPUS
uses CONFIG_IOAPIC
uses CONFIG_SMP
uses FALLBACK_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_ROM_STREAM
uses CONFIG_ROM_STREAM_START
uses PAYLOAD_SIZE
uses _ROMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses STACK_SIZE
uses HEAP_SIZE
uses USE_OPTION_TABLE
uses LB_CKS_RANGE_START
uses LB_CKS_RANGE_END
uses LB_CKS_LOC
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE=524288
###
### Build options
###
##
## Build code for the fallback boot
##
default HAVE_FALLBACK_BOOT=1
##
## Build code to reset the motherboard from linuxBIOS
##
default HAVE_HARD_RESET=1
default HARD_RESET_BUS=1
default HARD_RESET_DEVICE=4
default HARD_RESET_FUNCTION=0
##
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=12
##
## Build code to export an x86 MP table
## Useful for specifying IRQ routing values
##
default HAVE_MP_TABLE=1
##
## Build code to export a CMOS option table
##
default HAVE_OPTION_TABLE=1
##
## Move the default LinuxBIOS cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default LB_CKS_LOC=123
##
## Build code for SMP support
## Only worry about 2 micro processors
##
default CONFIG_SMP=1
default CONFIG_MAX_CPUS=2
##
## Build code to setup a generic IOAPIC
##
default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
default MAINBOARD_PART_NUMBER="HDAMA"
default MAINBOARD_VENDOR="ARIMA"
###
### LinuxBIOS layout values
###
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
default ROM_IMAGE_SIZE = 65536
##
## Use a small 8K stack
##
default STACK_SIZE=0x2000
##
## Use a small 16K heap
##
default HEAP_SIZE=0x8000
##
## Only use the option table in a normal image
##
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
##
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
@ -136,7 +16,6 @@ end
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_STREAM = 1
##
## Compute where this copy of linuxBIOS will start in the boot rom
@ -158,7 +37,6 @@ default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
##
arch i386 end
#cpu k8 end
##
## Build the objects we have code for in this directory.
@ -172,42 +50,41 @@ if HAVE_PIRQ_TABLE object irq_tables.o end
## Romcc output
##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
depends "./failover.E ./romcc"
action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c option_table.h "
action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "./auto.E ./romcc"
action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
##
mainboardinit cpu/i386/entry16.inc
mainboardinit cpu/i386/entry32.inc
mainboardinit cpu/i386/bist32.inc
ldscript /cpu/i386/entry16.lds
ldscript /cpu/i386/entry32.lds
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
##
## Build our reset vector (This is where linuxBIOS is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/i386/reset16.inc
ldscript /cpu/i386/reset16.lds
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
mainboardinit cpu/i386/reset32.inc
ldscript /cpu/i386/reset32.lds
mainboardinit cpu/x86/32bit/reset32.inc
ldscript /cpu/x86/32bit/reset32.lds
end
### Should this be in the northbridge code?
@ -219,11 +96,6 @@ mainboardinit arch/i386/lib/cpu_reset.inc
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
##
## Setup our mtrrs
##
mainboardinit cpu/k8/earlymtrr.inc
###
### This is the early phase of linuxBIOS startup
### Things are delicate and we test to see if we should
@ -241,9 +113,12 @@ end
##
## Setup RAM
##
mainboardinit cpu/k8/enable_mmx_sse.inc
mainboardinit cpu/x86/fpu/enable_fpu.inc
mainboardinit cpu/x86/mmx/enable_mmx.inc
mainboardinit cpu/x86/sse/enable_sse.inc
mainboardinit ./auto.inc
mainboardinit cpu/k8/disable_mmx_sse.inc
mainboardinit cpu/x86/sse/disable_sse.inc
mainboardinit cpu/x86/mmx/disable_mmx.inc
##
## Include the secondary Configuration files
@ -332,10 +207,3 @@ chip northbridge/amd/amdk8
end
end
##
## Include the old serial code for those few places that still need it.
##
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc
mainboardinit cpu/i386/bist32_fail.inc

4
src/mainboard/ibm/e325/Options.lb
View File

@ -117,6 +117,8 @@ default CONFIG_IOAPIC=1
##
default MAINBOARD_PART_NUMBER="E325"
default MAINBOARD_VENDOR="IBM"
#default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
#default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
###
### LinuxBIOS layout values
@ -133,7 +135,7 @@ default STACK_SIZE=0x2000
##
## Use a small 16K heap
##
default HEAP_SIZE=0x4000
default HEAP_SIZE=0x8000
##
## Only use the option table in a normal image

46
src/mainboard/ibm/e325/auto.c
View File

@ -6,7 +6,8 @@
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/smp/lapic.h>
#include <cpu/x86/lapic.h>
#include <arch/cpu.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
@ -15,13 +16,15 @@
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/k8/apic_timer.c"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#include "cpu/p6/boot_cpu.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
#include "superio/NSC/pc87366/pc87366_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
@ -127,12 +130,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#define FIRST_CPU 1
#define SECOND_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
static void main(void)
static void main(unsigned long bist)
{
/*
* GPIO28 of 8111 will control H0_MEMRESET_L
* GPIO29 of 8111 will control H1_MEMRESET_L
*/
static const struct mem_controller cpu[] = {
#if FIRST_CPU
{
@ -157,24 +156,30 @@ static void main(void)
},
#endif
};
int needs_reset;
enable_lapic();
init_timer();
if (cpu_init_detected()) {
asm("jmp __cpu_reset");
if (bist == 0) {
/* Skip this if there was a built in self test failure */
amd_early_mtrr_init();
enable_lapic();
init_timer();
/* Has this cpu already booted? */
if (cpu_init_detected()) {
asm volatile ("jmp __cpu_reset");
}
distinguish_cpu_resets();
if (!boot_cpu()) {
stop_this_cpu();
}
}
distinguish_cpu_resets();
if (!boot_cpu()) {
stop_this_cpu();
}
/* Setup the console */
pc87366_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
#if 0
print_pci_devices();
#endif
@ -224,5 +229,4 @@ static void main(void)
/* Check the first 1M */
ram_check(0x00000000, 0x001000000);
#endif
}

2
src/mainboard/ibm/e325/chip.h
View File

@ -1,4 +1,4 @@
extern struct chip_operations mainboard_ibm_e325_control;
extern struct chip_operations mainboard_ibm_e325_ops;
struct mainboard_ibm_e325_config {
int nothing;

7
src/mainboard/ibm/e325/mainboard.c
View File

@ -3,11 +3,8 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <arch/io.h>
#include "../../../northbridge/amd/amdk8/northbridge.h"
#include "chip.h"
struct chip_operations mainboard_ibm_e325_control = {
.name = "IBM E325 mainboard ",
struct chip_operations mainboard_ibm_e325_ops = {
CHIP_NAME("IBM E325 mainboard ")
};

26
src/mainboard/ibm/e325/mptable.c
View File

@ -4,7 +4,7 @@
#include <string.h>
#include <stdint.h>
void *smp_write_config_table(void *v, unsigned long * processor_map)
void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "IBM ";
@ -35,7 +35,7 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
mc->mpe_checksum = 0;
mc->reserved = 0;
smp_write_processors(mc, processor_map);
smp_write_processors(mc);
{
device_t dev;
@ -83,20 +83,22 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
{
device_t dev;
uint32_t base;
struct resource *res;
/* 8131-1 apic #3 */
dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
if (dev) {
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
base &= PCI_BASE_ADDRESS_MEM_MASK;
smp_write_ioapic(mc, 0x03, 0x11, base);
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 0x03, 0x11, res->base);
}
}
/* 8131-2 apic #4 */
dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
if (dev) {
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
base &= PCI_BASE_ADDRESS_MEM_MASK;
smp_write_ioapic(mc, 0x04, 0x11, base);
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 0x04, 0x11, res->base);
}
}
}
@ -164,10 +166,10 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
return smp_next_mpe_entry(mc);
}
unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr);
return (unsigned long)smp_write_config_table(v, processor_map);
return (unsigned long)smp_write_config_table(v);
}

174
src/mainboard/newisys/khepri/Config.lb
View File

@ -1,123 +1,3 @@
uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
uses HARD_RESET_BUS
uses HARD_RESET_DEVICE
uses HARD_RESET_FUNCTION
uses IRQ_SLOT_COUNT
uses HAVE_OPTION_TABLE
uses CONFIG_MAX_CPUS
uses CONFIG_IOAPIC
uses CONFIG_SMP
uses FALLBACK_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_ROM_STREAM
uses CONFIG_ROM_STREAM_START
uses PAYLOAD_SIZE
uses _ROMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses STACK_SIZE
uses HEAP_SIZE
uses USE_OPTION_TABLE
uses LB_CKS_RANGE_START
uses LB_CKS_RANGE_END
uses LB_CKS_LOC
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE=524288
###
### Build options
###
##
## Build code for the fallback boot
##
default HAVE_FALLBACK_BOOT=1
##
## Build code to reset the motherboard from linuxBIOS
##
default HAVE_HARD_RESET=1
default HARD_RESET_BUS=1
default HARD_RESET_DEVICE=4
default HARD_RESET_FUNCTION=0
##
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=9
##
## Build code to export an x86 MP table
## Useful for specifying IRQ routing values
##
default HAVE_MP_TABLE=1
##
## Build code to export a CMOS option table
##
default HAVE_OPTION_TABLE=1
##
## Move the default LinuxBIOS cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default LB_CKS_LOC=123
##
## Build code for SMP support
## Only worry about 2 micro processors
##
default CONFIG_SMP=1
default CONFIG_MAX_CPUS=2
##
## Build code to setup a generic IOAPIC
##
default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
default MAINBOARD_PART_NUMBER="Khepri 2100"
default MAINBOARD_VENDOR="Newisys"
###
### LinuxBIOS layout values
###
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
default ROM_IMAGE_SIZE = 65536
##
## Use a small 8K stack
##
default STACK_SIZE=0x2000
##
## Use a small 16K heap
##
default HEAP_SIZE=0x4000
##
## Only use the option table in a normal image
##
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
##
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
@ -136,7 +16,6 @@ end
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_STREAM = 1
##
## Compute where this copy of linuxBIOS will start in the boot rom
@ -158,7 +37,6 @@ default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
##
arch i386 end
#cpu k8 end
##
## Build the objects we have code for in this directory.
@ -174,42 +52,41 @@ dir /drivers/trident/blade3d
## Romcc output
##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
depends "./failover.E ./romcc"
action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c option_table.h"
action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "./auto.E ./romcc"
action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
##
mainboardinit cpu/i386/entry16.inc
mainboardinit cpu/i386/entry32.inc
mainboardinit cpu/i386/bist32.inc
ldscript /cpu/i386/entry16.lds
ldscript /cpu/i386/entry32.lds
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
##
## Build our reset vector (This is where linuxBIOS is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/i386/reset16.inc
ldscript /cpu/i386/reset16.lds
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
mainboardinit cpu/i386/reset32.inc
ldscript /cpu/i386/reset32.lds
mainboardinit cpu/x86/32bit/reset32.inc
ldscript /cpu/x86/32bit/reset32.lds
end
### Should this be in the northbridge code?
@ -221,11 +98,6 @@ mainboardinit arch/i386/lib/cpu_reset.inc
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
##
## Setup our mtrrs
##
mainboardinit cpu/k8/earlymtrr.inc
###
### This is the early phase of linuxBIOS startup
### Things are delicate and we test to see if we should
@ -243,9 +115,12 @@ end
##
## Setup RAM
##
mainboardinit cpu/k8/enable_mmx_sse.inc
mainboardinit cpu/x86/fpu/enable_fpu.inc
mainboardinit cpu/x86/mmx/enable_mmx.inc
mainboardinit cpu/x86/sse/enable_sse.inc
mainboardinit ./auto.inc
mainboardinit cpu/k8/disable_mmx_sse.inc
mainboardinit cpu/x86/sse/disable_sse.inc
mainboardinit cpu/x86/mmx/disable_mmx.inc
##
## Include the secondary Configuration files
@ -334,10 +209,3 @@ chip northbridge/amd/amdk8
end
end
##
## Include the old serial code for those few places that still need it.
##
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc
mainboardinit cpu/i386/bist32_fail.inc

47
src/mainboard/newisys/khepri/auto.c
View File

@ -1,4 +1,6 @@
#define ASSEMBLY 1
#undef MAXIMUM_CONSOLE_LOGLEVEL
#undef DEFAULT_CONSOLE_LOGLEVEL
#define MAXIMUM_CONSOLE_LOGLEVEL 9
#define DEFAULT_CONSOLE_LOGLEVEL 9
@ -7,7 +9,8 @@
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/smp/lapic.h>
#include <cpu/x86/lapic.h>
#include <arch/cpu.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
@ -16,13 +19,15 @@
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/k8/apic_timer.c"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#include "cpu/p6/boot_cpu.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
#include "superio/NSC/pc87360/pc87360_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
@ -126,14 +131,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "sdram/generic_sdram.c"
#include "resourcemap.c" /* newisys khepri does not want the default */
/* newisys khepri does not want the default */
#include "resourcemap.c"
static void main(void)
static void main(unsigned long bist)
{
/*
* GPIO28 of 8111 will control H0_MEMRESET_L
* GPIO29 of 8111 will control H1_MEMRESET_L
*/
static const struct mem_controller cpu[] = {
{
.node_id = 0,
@ -154,19 +156,30 @@ static void main(void)
.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
},
};
int needs_reset;
enable_lapic();
init_timer();
if (cpu_init_detected()) {
asm("jmp __cpu_reset");
}
distinguish_cpu_resets();
if (!boot_cpu()) {
stop_this_cpu();
if (bist == 0) {
/* Skip this if there was a built in self test failure */
amd_early_mtrr_init();
enable_lapic();
init_timer();
/* Has this cpu already booted? */
if (cpu_init_detected()) {
asm volatile ("jmp __cpu_reset");
}
distinguish_cpu_resets();
if (!boot_cpu()) {
stop_this_cpu();
}
}
/* Setup the console */
pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
setup_khepri_resource_map();
needs_reset = setup_coherent_ht_domain();
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);

2
src/mainboard/newisys/khepri/chip.h
View File

@ -1,4 +1,4 @@
extern struct chip_operations mainboard_newisys_khepri_control;
extern struct chip_operations mainboard_newisys_khepri_ops;
struct mainboard_newisys_khepri_config {
int nothing;

7
src/mainboard/newisys/khepri/mainboard.c
View File

@ -3,12 +3,9 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <arch/io.h>
#include "../../../northbridge/amd/amdk8/northbridge.h"
#include "chip.h"
struct chip_operations mainboard_newisys_khepri_control = {
.name = "Newisys Khepri mainboard ",
struct chip_operations mainboard_newisys_khepri_ops = {
CHIP_NAME("Newisys Khepri mainboard ")
};

25
src/mainboard/newisys/khepri/mptable.c
View File

@ -4,7 +4,7 @@
#include <string.h>
#include <stdint.h>
void *smp_write_config_table(void *v, unsigned long * processor_map)
void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "NEWISYS ";
@ -33,7 +33,7 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
mc->mpe_checksum = 0;
mc->reserved = 0;
smp_write_processors(mc, processor_map);
smp_write_processors(mc);
{
device_t dev;
@ -86,20 +86,22 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
{
device_t dev;
uint32_t base;
struct resource *res;
/* 8131 apic 3 */
dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
if (dev) {
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
base &= PCI_BASE_ADDRESS_MEM_MASK;
smp_write_ioapic(mc, 0x03, 0x11, base);
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 0x03, 0x11, res->base);
}
}
/* 8131 apic 4 */
dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
if (dev) {
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
base &= PCI_BASE_ADDRESS_MEM_MASK;
smp_write_ioapic(mc, 0x04, 0x11, base);
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 0x04, 0x11, res->base);
}
}
}
@ -216,17 +218,16 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
/* Compute the checksums */
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk_debug("Wrote the mp table end at: %p - %p\n",
mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr);
return (unsigned long)smp_write_config_table(v, processor_map);
return (unsigned long)smp_write_config_table(v);
}

19
src/mainboard/technologic/ts5300/Config.lb
View File

@ -134,22 +134,22 @@ driver mainboard.o
## Romcc output
##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
depends "./failover.E ./romcc"
action "./romcc -O -mcpu=c3 -o failover.inc --label-prefix=failover ./failover.E"
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -E -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "./auto.E ./romcc"
action "./romcc -O -mcpu=c3 ./auto.E "
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
##
@ -218,5 +218,6 @@ chip northbridge/amd/sc520
register "enable_keyboard" = "0"
register "enable_nvram" = "1"
end
chip cpu/amd/sc520
chip cpu/amd/sc520
end
end

28
src/mainboard/technologic/ts5300/mainboard.c
View File

@ -3,35 +3,9 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <arch/io.h>
#include "chip.h"
static int
mainboard_scan_bus(device_t root, int maxbus)
{
int retval;
printk_spew("%s: root %p maxbus %d\n", __FUNCTION__, root, maxbus);
retval = pci_scan_bus(root->bus, 0, 0xff, maxbus);
printk_spew("DONE %s: return %d\n", __FUNCTION__, maxbus);
return maxbus;
}
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = root_dev_enable_resources,
.init = root_dev_init,
.scan_bus = mainboard_scan_bus,
};
static void enable_dev(device_t dev)
{
dev->ops = &mainbaord_operations;
}
struct chip_operations mainboard_technologic_ts5300_control = {
.enable_dev = enable_dev,
.name = "Technologic Systems TS5300 mainboard ",
CHIP_NAME("Technologic Systems TS5300 mainboard ")
};

26
src/mainboard/tyan/s2735/mainboard.c
View File

@ -119,30 +119,6 @@ static void vga_fixup(void) {
}
*/
static int
mainboard_scan_bus(device_t root, int maxbus)
{
int retval;
printk_spew("%s: root %p maxbus %d\n", __FUNCTION__, root, maxbus);
retval = pci_scan_bus(root->bus, 0, 0xff, maxbus);
printk_spew("DONE %s: return %d\n", __FUNCTION__, maxbus);
return maxbus;
}
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = root_dev_enable_resources,
.init = root_dev_init,
.scan_bus = mainboard_scan_bus,
};
static void enable_dev(device_t dev)
{
dev->ops = &mainboard_operations;
}
struct chip_operations mainboard_tyan_s2735_ops = {
.enable_dev = enable_dev,
CHIP_NAME("Tyan s2735 mainboard")
};

107
src/mainboard/tyan/s2850/mainboard.c
View File

@ -163,111 +163,6 @@ enable(struct chip *chip, enum chip_pass pass)
}
#endif
#undef DEBUG
#define DEBUG 0
#if DEBUG
static void debug_init(device_t dev)
{
unsigned bus;
unsigned devfn;
#if 0
for(bus = 0; bus < 256; bus++) {
for(devfn = 0; devfn < 256; devfn++) {
int i;
dev = dev_find_slot(bus, devfn);
if (!dev) {
continue;
}
if (!dev->enabled) {
continue;
}
printk_info("%02x:%02x.%0x aka %s\n",
bus, devfn >> 3, devfn & 7, dev_path(dev));
for(i = 0; i < 256; i++) {
if ((i & 0x0f) == 0) {
printk_info("%02x:", i);
}
printk_info(" %02x", pci_read_config8(dev, i));
if ((i & 0x0f) == 0xf) {
printk_info("\n");
}
}
printk_info("\n");
}
}
#endif
#if 0
msr_t msr;
unsigned index;
unsigned eax, ebx, ecx, edx;
index = 0x80000007;
printk_debug("calling cpuid 0x%08x\n", index);
asm volatile(
"cpuid"
: "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
: "a" (index)
);
printk_debug("cpuid[%08x]: %08x %08x %08x %08x\n",
index, eax, ebx, ecx, edx);
if (edx & (3 << 1)) {
index = 0xC0010042;
printk_debug("Reading msr: 0x%08x\n", index);
msr = rdmsr(index);
printk_debug("msr[0x%08x]: 0x%08x%08x\n",
index, msr.hi, msr.hi);
}
#endif
}
static void debug_noop(device_t dummy)
{
}
static struct device_operations debug_operations = {
.read_resources = debug_noop,
.set_resources = debug_noop,
.enable_resources = debug_noop,
.init = debug_init,
};
static unsigned int scan_root_bus(device_t root, unsigned int max)
{
struct device_path path;
device_t debug;
max = root_dev_scan_bus(root, max);
path.type = DEVICE_PATH_PNP;
path.u.pnp.port = 0;
path.u.pnp.device = 0;
debug = alloc_dev(&root->link[1], &path);
debug->ops = &debug_operations;
return max;
}
#endif
static void mainboard_init(device_t dev)
{
root_dev_init(dev);
// do_verify_cpu_voltages();
}
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = root_dev_enable_resources,
.init = mainboard_init,
#if !DEBUG
.scan_bus = root_dev_scan_bus,
#else
.scan_bus = scan_root_bus,
#endif
.enable = 0,
};
static void enable_dev(struct device *dev)
{
dev_root.ops = &mainboard_operations;
}
struct chip_operations mainboard_tyan_s2850_ops = {
.enable_dev = enable_dev,
CHIP_NAME("Tyan s2850 mainboard")
};

107
src/mainboard/tyan/s2880/mainboard.c
View File

@ -163,111 +163,6 @@ enable(struct chip *chip, enum chip_pass pass)
}
#endif
#undef DEBUG
#define DEBUG 0
#if DEBUG
static void debug_init(device_t dev)
{
unsigned bus;
unsigned devfn;
#if 0
for(bus = 0; bus < 256; bus++) {
for(devfn = 0; devfn < 256; devfn++) {
int i;
dev = dev_find_slot(bus, devfn);
if (!dev) {
continue;
}
if (!dev->enabled) {
continue;
}
printk_info("%02x:%02x.%0x aka %s\n",
bus, devfn >> 3, devfn & 7, dev_path(dev));
for(i = 0; i < 256; i++) {
if ((i & 0x0f) == 0) {
printk_info("%02x:", i);
}
printk_info(" %02x", pci_read_config8(dev, i));
if ((i & 0x0f) == 0xf) {
printk_info("\n");
}
}
printk_info("\n");
}
}
#endif
#if 0
msr_t msr;
unsigned index;
unsigned eax, ebx, ecx, edx;
index = 0x80000007;
printk_debug("calling cpuid 0x%08x\n", index);
asm volatile(
"cpuid"
: "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
: "a" (index)
);
printk_debug("cpuid[%08x]: %08x %08x %08x %08x\n",
index, eax, ebx, ecx, edx);
if (edx & (3 << 1)) {
index = 0xC0010042;
printk_debug("Reading msr: 0x%08x\n", index);
msr = rdmsr(index);
printk_debug("msr[0x%08x]: 0x%08x%08x\n",
index, msr.hi, msr.hi);
}
#endif
}
static void debug_noop(device_t dummy)
{
}
static struct device_operations debug_operations = {
.read_resources = debug_noop,
.set_resources = debug_noop,
.enable_resources = debug_noop,
.init = debug_init,
};
static unsigned int scan_root_bus(device_t root, unsigned int max)
{
struct device_path path;
device_t debug;
max = root_dev_scan_bus(root, max);
path.type = DEVICE_PATH_PNP;
path.u.pnp.port = 0;
path.u.pnp.device = 0;
debug = alloc_dev(&root->link[1], &path);
debug->ops = &debug_operations;
return max;
}
#endif
static void mainboard_init(device_t dev)
{
root_dev_init(dev);
// do_verify_cpu_voltages();
}
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = root_dev_enable_resources,
.init = mainboard_init,
#if !DEBUG
.scan_bus = root_dev_scan_bus,
#else
.scan_bus = scan_root_bus,
#endif
.enable = 0,
};
static void enable_dev(struct device *dev)
{
dev_root.ops = &mainboard_operations;
}
struct chip_operations mainboard_tyan_s2880_ops = {
.enable_dev = enable_dev,
CHIP_NAME("Tayn s2880 mainboard")
};

107
src/mainboard/tyan/s2881/mainboard.c
View File

@ -163,111 +163,6 @@ enable(struct chip *chip, enum chip_pass pass)
}
#endif
#undef DEBUG
#define DEBUG 0
#if DEBUG
static void debug_init(device_t dev)
{
unsigned bus;
unsigned devfn;
#if 0
for(bus = 0; bus < 256; bus++) {
for(devfn = 0; devfn < 256; devfn++) {
int i;
dev = dev_find_slot(bus, devfn);
if (!dev) {
continue;
}
if (!dev->enabled) {
continue;
}
printk_info("%02x:%02x.%0x aka %s\n",
bus, devfn >> 3, devfn & 7, dev_path(dev));
for(i = 0; i < 256; i++) {
if ((i & 0x0f) == 0) {
printk_info("%02x:", i);
}
printk_info(" %02x", pci_read_config8(dev, i));
if ((i & 0x0f) == 0xf) {
printk_info("\n");
}
}
printk_info("\n");
}
}
#endif
#if 0
msr_t msr;
unsigned index;
unsigned eax, ebx, ecx, edx;
index = 0x80000007;
printk_debug("calling cpuid 0x%08x\n", index);
asm volatile(
"cpuid"
: "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
: "a" (index)
);
printk_debug("cpuid[%08x]: %08x %08x %08x %08x\n",
index, eax, ebx, ecx, edx);
if (edx & (3 << 1)) {
index = 0xC0010042;
printk_debug("Reading msr: 0x%08x\n", index);
msr = rdmsr(index);
printk_debug("msr[0x%08x]: 0x%08x%08x\n",
index, msr.hi, msr.hi);
}
#endif
}
static void debug_noop(device_t dummy)
{
}
static struct device_operations debug_operations = {
.read_resources = debug_noop,
.set_resources = debug_noop,
.enable_resources = debug_noop,
.init = debug_init,
};
static unsigned int scan_root_bus(device_t root, unsigned int max)
{
struct device_path path;
device_t debug;
max = root_dev_scan_bus(root, max);
path.type = DEVICE_PATH_PNP;
path.u.pnp.port = 0;
path.u.pnp.device = 0;
debug = alloc_dev(&root->link[1], &path);
debug->ops = &debug_operations;
return max;
}
#endif
static void mainboard_init(device_t dev)
{
root_dev_init(dev);
// do_verify_cpu_voltages();
}
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = root_dev_enable_resources,
.init = mainboard_init,
#if !DEBUG
.scan_bus = root_dev_scan_bus,
#else
.scan_bus = scan_root_bus,
#endif
.enable = 0,
};
static void enable_dev(struct device *dev)
{
dev_root.ops = &mainboard_operations;
}
struct chip_operations mainboard_tyan_s2881_ops = {
.enable_dev = enable_dev,
CHIP_NAME("Tyan s2881 mainboard")
};

5
src/mainboard/tyan/s2882/auto.c
View File

@ -126,11 +126,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
//#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "northbridge/amd/amdk8/resourcemap.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
#include "northbridge/amd/amdk8/resourcemap.c"
#define FIRST_CPU 1
@ -196,7 +195,7 @@ static void main(unsigned long bist)
console_init();
/* Halt if there was a built in self test failure */
// report_bist_failure(bist);
report_bist_failure(bist);
setup_default_resource_map();
needs_reset = setup_coherent_ht_domain();

107
src/mainboard/tyan/s2882/mainboard.c
View File

@ -163,111 +163,6 @@ enable(struct chip *chip, enum chip_pass pass)
}
#endif
#undef DEBUG
#define DEBUG 0
#if DEBUG
static void debug_init(device_t dev)
{
unsigned bus;
unsigned devfn;
#if 0
for(bus = 0; bus < 256; bus++) {
for(devfn = 0; devfn < 256; devfn++) {
int i;
dev = dev_find_slot(bus, devfn);
if (!dev) {
continue;
}
if (!dev->enabled) {
continue;
}
printk_info("%02x:%02x.%0x aka %s\n",
bus, devfn >> 3, devfn & 7, dev_path(dev));
for(i = 0; i < 256; i++) {
if ((i & 0x0f) == 0) {
printk_info("%02x:", i);
}
printk_info(" %02x", pci_read_config8(dev, i));
if ((i & 0x0f) == 0xf) {
printk_info("\n");
}
}
printk_info("\n");
}
}
#endif
#if 0
msr_t msr;
unsigned index;
unsigned eax, ebx, ecx, edx;
index = 0x80000007;
printk_debug("calling cpuid 0x%08x\n", index);
asm volatile(
"cpuid"
: "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
: "a" (index)
);
printk_debug("cpuid[%08x]: %08x %08x %08x %08x\n",
index, eax, ebx, ecx, edx);
if (edx & (3 << 1)) {
index = 0xC0010042;
printk_debug("Reading msr: 0x%08x\n", index);
msr = rdmsr(index);
printk_debug("msr[0x%08x]: 0x%08x%08x\n",
index, msr.hi, msr.hi);
}
#endif
}
static void debug_noop(device_t dummy)
{
}
static struct device_operations debug_operations = {
.read_resources = debug_noop,
.set_resources = debug_noop,
.enable_resources = debug_noop,
.init = debug_init,
};
static unsigned int scan_root_bus(device_t root, unsigned int max)
{
struct device_path path;
device_t debug;
max = root_dev_scan_bus(root, max);
path.type = DEVICE_PATH_PNP;
path.u.pnp.port = 0;
path.u.pnp.device = 0;
debug = alloc_dev(&root->link[1], &path);
debug->ops = &debug_operations;
return max;
}
#endif
static void mainboard_init(device_t dev)
{
root_dev_init(dev);
// do_verify_cpu_voltages();
}
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = root_dev_enable_resources,
.init = mainboard_init,
#if !DEBUG
.scan_bus = root_dev_scan_bus,
#else
.scan_bus = scan_root_bus,
#endif
.enable = 0,
};
static void enable_dev(struct device *dev)
{
dev_root.ops = &mainboard_operations;
}
struct chip_operations mainboard_tyan_s2882_ops = {
.enable_dev = enable_dev,
CHIP_NAME("Tyan s2882 mainboard")
};

107
src/mainboard/tyan/s2885/mainboard.c
View File

@ -163,111 +163,6 @@ enable(struct chip *chip, enum chip_pass pass)
}
#endif
#undef DEBUG
#define DEBUG 0
#if DEBUG
static void debug_init(device_t dev)
{
unsigned bus;
unsigned devfn;
#if 0
for(bus = 0; bus < 256; bus++) {
for(devfn = 0; devfn < 256; devfn++) {
int i;
dev = dev_find_slot(bus, devfn);
if (!dev) {
continue;
}
if (!dev->enabled) {
continue;
}
printk_info("%02x:%02x.%0x aka %s\n",
bus, devfn >> 3, devfn & 7, dev_path(dev));
for(i = 0; i < 256; i++) {
if ((i & 0x0f) == 0) {
printk_info("%02x:", i);
}
printk_info(" %02x", pci_read_config8(dev, i));
if ((i & 0x0f) == 0xf) {
printk_info("\n");
}
}
printk_info("\n");
}
}
#endif
#if 0
msr_t msr;
unsigned index;
unsigned eax, ebx, ecx, edx;
index = 0x80000007;
printk_debug("calling cpuid 0x%08x\n", index);
asm volatile(
"cpuid"
: "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
: "a" (index)
);
printk_debug("cpuid[%08x]: %08x %08x %08x %08x\n",
index, eax, ebx, ecx, edx);
if (edx & (3 << 1)) {
index = 0xC0010042;
printk_debug("Reading msr: 0x%08x\n", index);
msr = rdmsr(index);
printk_debug("msr[0x%08x]: 0x%08x%08x\n",
index, msr.hi, msr.hi);
}
#endif
}
static void debug_noop(device_t dummy)
{
}
static struct device_operations debug_operations = {
.read_resources = debug_noop,
.set_resources = debug_noop,
.enable_resources = debug_noop,
.init = debug_init,
};
static unsigned int scan_root_bus(device_t root, unsigned int max)
{
struct device_path path;
device_t debug;
max = root_dev_scan_bus(root, max);
path.type = DEVICE_PATH_PNP;
path.u.pnp.port = 0;
path.u.pnp.device = 0;
debug = alloc_dev(&root->link[1], &path);
debug->ops = &debug_operations;
return max;
}
#endif
static void mainboard_init(device_t dev)
{
root_dev_init(dev);
// do_verify_cpu_voltages();
}
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = root_dev_enable_resources,
.init = mainboard_init,
#if !DEBUG
.scan_bus = root_dev_scan_bus,
#else
.scan_bus = scan_root_bus,
#endif
.enable = 0,
};
static void enable_dev(struct device *dev)
{
dev_root.ops = &mainboard_operations;
}
struct chip_operations mainboard_tyan_s2885_ops = {
.enable_dev = enable_dev,
CHIP_NAME("Tyan s2885 mainboard")
};

2
src/mainboard/tyan/s4880/auto.c
View File

@ -256,7 +256,7 @@ static void main(unsigned long bist)
console_init();
/* Halt if there was a built in self test failure */
// report_bist_failure(bist);
report_bist_failure(bist);
setup_s4880_resource_map();
needs_reset = setup_coherent_ht_domain();

107
src/mainboard/tyan/s4880/mainboard.c
View File

@ -163,111 +163,6 @@ enable(struct chip *chip, enum chip_pass pass)
}
#endif
#undef DEBUG
#define DEBUG 0
#if DEBUG
static void debug_init(device_t dev)
{
unsigned bus;
unsigned devfn;
#if 0
for(bus = 0; bus < 256; bus++) {
for(devfn = 0; devfn < 256; devfn++) {
int i;
dev = dev_find_slot(bus, devfn);
if (!dev) {
continue;
}
if (!dev->enabled) {
continue;
}
printk_info("%02x:%02x.%0x aka %s\n",
bus, devfn >> 3, devfn & 7, dev_path(dev));
for(i = 0; i < 256; i++) {
if ((i & 0x0f) == 0) {
printk_info("%02x:", i);
}
printk_info(" %02x", pci_read_config8(dev, i));
if ((i & 0x0f) == 0xf) {
printk_info("\n");
}
}
printk_info("\n");
}
}
#endif
#if 0
msr_t msr;
unsigned index;
unsigned eax, ebx, ecx, edx;
index = 0x80000007;
printk_debug("calling cpuid 0x%08x\n", index);
asm volatile(
"cpuid"
: "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
: "a" (index)
);
printk_debug("cpuid[%08x]: %08x %08x %08x %08x\n",
index, eax, ebx, ecx, edx);
if (edx & (3 << 1)) {
index = 0xC0010042;
printk_debug("Reading msr: 0x%08x\n", index);
msr = rdmsr(index);
printk_debug("msr[0x%08x]: 0x%08x%08x\n",
index, msr.hi, msr.hi);
}
#endif
}
static void debug_noop(device_t dummy)
{
}
static struct device_operations debug_operations = {
.read_resources = debug_noop,
.set_resources = debug_noop,
.enable_resources = debug_noop,
.init = debug_init,
};
static unsigned int scan_root_bus(device_t root, unsigned int max)
{
struct device_path path;
device_t debug;
max = root_dev_scan_bus(root, max);
path.type = DEVICE_PATH_PNP;
path.u.pnp.port = 0;
path.u.pnp.device = 0;
debug = alloc_dev(&root->link[1], &path);
debug->ops = &debug_operations;
return max;
}
#endif
static void mainboard_init(device_t dev)
{
root_dev_init(dev);
// do_verify_cpu_voltages();
}
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = root_dev_enable_resources,
.init = mainboard_init,
#if !DEBUG
.scan_bus = root_dev_scan_bus,
#else
.scan_bus = scan_root_bus,
#endif
.enable = 0,
};
static void enable_dev(struct device *dev)
{
dev_root.ops = &mainboard_operations;
}
struct chip_operations mainboard_tyan_s4880_ops = {
.enable_dev = enable_dev,
CHIP_NAME("Tyan s4880 mainboard")
};

108
src/mainboard/tyan/s4882/mainboard.c
View File

@ -162,112 +162,6 @@ enable(struct chip *chip, enum chip_pass pass)
}
#endif
#undef DEBUG
#define DEBUG 0
#if DEBUG
static void debug_init(device_t dev)
{
unsigned bus;
unsigned devfn;
#if 0
for(bus = 0; bus < 256; bus++) {
for(devfn = 0; devfn < 256; devfn++) {
int i;
dev = dev_find_slot(bus, devfn);
if (!dev) {
continue;
}
if (!dev->enabled) {
continue;
}
printk_info("%02x:%02x.%0x aka %s\n",
bus, devfn >> 3, devfn & 7, dev_path(dev));
for(i = 0; i < 256; i++) {
if ((i & 0x0f) == 0) {
printk_info("%02x:", i);
}
printk_info(" %02x", pci_read_config8(dev, i));
if ((i & 0x0f) == 0xf) {
printk_info("\n");
}
}
printk_info("\n");
}
}
#endif
#if 0
msr_t msr;
unsigned index;
unsigned eax, ebx, ecx, edx;
index = 0x80000007;
printk_debug("calling cpuid 0x%08x\n", index);
asm volatile(
"cpuid"
: "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
: "a" (index)
);
printk_debug("cpuid[%08x]: %08x %08x %08x %08x\n",
index, eax, ebx, ecx, edx);
if (edx & (3 << 1)) {
index = 0xC0010042;
printk_debug("Reading msr: 0x%08x\n", index);
msr = rdmsr(index);
printk_debug("msr[0x%08x]: 0x%08x%08x\n",
index, msr.hi, msr.hi);
}
#endif
}
static void debug_noop(device_t dummy)
{
}
static struct device_operations debug_operations = {
.read_resources = debug_noop,
.set_resources = debug_noop,
.enable_resources = debug_noop,
.init = debug_init,
};
static unsigned int scan_root_bus(device_t root, unsigned int max)
{
struct device_path path;
device_t debug;
max = root_dev_scan_bus(root, max);
path.type = DEVICE_PATH_PNP;
path.u.pnp.port = 0;
path.u.pnp.device = 0;
debug = alloc_dev(&root->link[1], &path);
debug->ops = &debug_operations;
return max;
}
#endif
static void mainboard_init(device_t dev)
{
root_dev_init(dev);
// do_verify_cpu_voltages();
}
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = root_dev_enable_resources,
.init = mainboard_init,
#if !DEBUG
.scan_bus = root_dev_scan_bus,
#else
.scan_bus = scan_root_bus,
#endif
.enable = 0,
};
static void enable_dev(struct device *dev)
{
dev_root.ops = &mainboard_operations;
}
struct chip_operations mainboard_tyan_s4882_ops = {
.enable_dev = enable_dev,
CHIP_NAME("Tyan s4882 mainboard")
};

171
src/mainboard/via/epia-m/Config.lb
View File

@ -1,87 +1,3 @@
uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
uses HAVE_OPTION_TABLE
uses USE_OPTION_TABLE
uses CONFIG_ROM_STREAM
uses IRQ_SLOT_COUNT
uses MAINBOARD
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
uses HEAP_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_ROM_STREAM_START
uses PAYLOAD_SIZE
uses _ROMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses HAVE_MP_TABLE
uses HAVE_ACPI_TABLES
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256*1024
###
### Build options
###
##
## Build code for the fallback boot
##
default HAVE_FALLBACK_BOOT=1
##
## no MP table
##
default HAVE_MP_TABLE=0
##
## Build code to reset the motherboard from linuxBIOS
##
default HAVE_HARD_RESET=1
##
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=5
object irq_tables.o
##
## Build code to export a CMOS option table
##
default HAVE_OPTION_TABLE=1
###
### LinuxBIOS layout values
###
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
default ROM_IMAGE_SIZE = 65536
##
## Use a small 8K stack
##
default STACK_SIZE=0x2000
##
## Use a small 16K heap
##
default HEAP_SIZE=0x4000
##
## Only use the option table in a normal image
##
#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
default USE_OPTION_TABLE = 0
##
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
@ -100,7 +16,6 @@ end
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_STREAM = 1
##
## Compute where this copy of linuxBIOS will start in the boot rom
@ -127,8 +42,8 @@ arch i386 end
## Build the objects we have code for in this directory.
##
driver mainboard.o
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
if HAVE_ACPI_TABLES
@ -140,41 +55,41 @@ end
## Romcc output
##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
depends "./failover.E ./romcc"
action "./romcc -O -mcpu=c3 -o failover.inc --label-prefix=failover ./failover.E"
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "./auto.E ./romcc"
action "./romcc -O -mcpu=c3 ./auto.E "
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
##
mainboardinit cpu/i386/entry16.inc
mainboardinit cpu/i386/entry32.inc
ldscript /cpu/i386/entry16.lds
ldscript /cpu/i386/entry32.lds
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
##
## Build our reset vector (This is where linuxBIOS is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/i386/reset16.inc
ldscript /cpu/i386/reset16.lds
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
mainboardinit cpu/i386/reset32.inc
ldscript /cpu/i386/reset32.lds
mainboardinit cpu/x86/32bit/reset32.inc
ldscript /cpu/x86/32bit/reset32.lds
end
### Should this be in the northbridge code?
@ -186,11 +101,6 @@ mainboardinit arch/i386/lib/cpu_reset.inc
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
##
## Setup our mtrrs
##
# mainboardinit cpu/p6/earlymtrr.inc
###
### This is the early phase of linuxBIOS startup
### Things are delicate and we test to see if we should
@ -208,7 +118,10 @@ end
##
## Setup RAM
##
mainboardinit cpu/x86/fpu/enable_fpu.inc
mainboardinit cpu/x86/mmx/enable_mmx.inc
mainboardinit ./auto.inc
mainboardinit cpu/x86/mmx/disable_mmx.inc
##
## Include the secondary Configuration files
@ -216,30 +129,24 @@ mainboardinit ./auto.inc
dir /pc80
config chip.h
northbridge via/vt8623 "vt8623"
southbridge via/vt8235 "vt8235"
register "enable_usb" = "0"
register "enable_native_ide" = "0"
register "enable_com_ports" = "1"
register "enable_keyboard" = "0"
register "enable_nvram" = "1"
end
southbridge ricoh/rl5c476 "rl5c476"
end
superio via/vt1211 "vt1211"
register "enable_com_ports" = "1"
register "enable_hwmon" = "1"
register "enable_lpt" = "1"
register "enable_fdc" = "1"
chip northbridge/via/vt8623
device pci_domain 0 on
chip southbridge/via/vt8235
register "enable_usb" = "0"
register "enable_native_ide" = "0"
register "enable_com_ports" = "1"
register "enable_keyboard" = "0"
register "enable_nvram" = "1"
end
chip southbridge/ricoh/rl5c476
end
chip superio/via/vt1211
register "enable_com_ports" = "1"
register "enable_hwmon" = "1"
register "enable_lpt" = "1"
register "enable_fdc" = "1"
end
chip cpu/via/model_centaur
end
end
end
cpu p6 "cpu0"
end
##
## Include the old serial code for those few places that still need it.
##
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc

27
src/mainboard/via/epia-m/auto.c
View File

@ -3,7 +3,9 @@
#include <stdint.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <cpu/p6/apic.h>
#if 0
#include <cpu/x86/lapic.h>
#endif
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
@ -12,7 +14,8 @@
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#include "northbridge/via/vt8623/raminit.h"
#include "cpu/p6/earlymtrr.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
/*
*/
@ -24,7 +27,7 @@ void udelay(int usecs)
}
#include "lib/delay.c"
#include "cpu/p6/boot_cpu.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "debug.c"
#include "southbridge/via/vt8235/vt8235_early_smbus.c"
@ -95,10 +98,22 @@ static void enable_shadow_ram(void)
pci_write_config8(dev, 0x63, shadowreg);
}
static void main(void)
static void main(unsigned long bist)
{
unsigned long x;
device_t dev;
if (bist == 0) {
early_mtrr_init();
}
enable_vt8235_serial();
uart_init();
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
/* init_timer();*/
outb(5, 0x80);
@ -108,10 +123,7 @@ static void main(void)
outb(5, 0x80);
enable_smbus();
enable_vt8235_serial();
uart_init();
console_init();
enable_mainboard_devices();
enable_shadow_ram();
@ -144,5 +156,4 @@ static void main(void)
ram_check(check_addrs[i].lo, check_addrs[i].hi);
}
#endif
early_mtrr_init();
}

2
src/mainboard/via/epia-m/chip.h
View File

@ -1,4 +1,4 @@
extern struct chip_operations mainboard_via_epia_m_control;
extern struct chip_operations mainboard_via_epia_m_ops;
struct mainboard_via_epia_m_config {
int nothing;

37
src/mainboard/via/epia-m/failover.c
View File

@ -5,25 +5,28 @@
#include <arch/io.h>
#include "arch/romcc_io.h"
#include "pc80/mc146818rtc_early.c"
#include "cpu/p6/boot_cpu.c"
static void main(void)
static unsigned long main(unsigned long bist)
{
/* for now, just always assume failure */
#if 0
/* Is this a cpu reset? */
if (cpu_init_detected()) {
if (last_boot_normal()) {
asm("jmp __normal_image");
} else {
asm("jmp __cpu_reset");
}
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
asm("jmp __normal_image");
if (do_normal_boot()) {
goto normal_image;
}
#endif
else {
goto fallback_image;
}
normal_image:
asm volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
: /* clobbers */
);
cpu_reset:
asm volatile ("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
: /* clobbers */
);
fallback_image:
return bist;
}

35
src/mainboard/via/epia-m/mainboard.c
View File

@ -3,24 +3,13 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <arch/io.h>
#include "chip.h"
void vga_enable_console();
static int
mainboard_scan_bus(device_t root, int maxbus)
{
int retval;
printk_spew("%s: root %p maxbus %d\n", __FUNCTION__, root, maxbus);
retval = pci_scan_bus(root->bus, 0, 0xff, maxbus);
printk_spew("DONE %s: return %d\n", __FUNCTION__, maxbus);
return maxbus;
}
void vga_fixup(void) {
static void vga_fixup(void) {
// we do this right here because:
// - all the hardware is working, and some VGA bioses seem to need
// that
@ -36,7 +25,7 @@ void vga_fixup(void) {
}
void write_protect_vgabios(void)
static void write_protect_vgabios(void)
{
device_t dev;
@ -44,25 +33,9 @@ void write_protect_vgabios(void)
dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3123, 0);
if(dev)
pci_write_config8(dev, 0x61, 0xaa);
}
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = root_dev_enable_resources,
.init = root_dev_init,
.scan_bus = mainboard_scan_bus,
.enable = 0,
};
static void enable_dev(device_t dev)
{
dev->ops = &mainboard_operations;
}
struct chip_operations mainboard_via_epia_m_control = {
.enable_dev = enable_dev,
.name = "VIA EPIA-M mainboard ",
struct chip_operations mainboard_via_epia_m_ops = {
CHIP_NAME("VIA EPIA-M mainboard ")
};

34
src/mainboard/via/epia/Config.lb
View File

@ -42,7 +42,6 @@ arch i386 end
## Build the objects we have code for in this directory.
##
driver mainboard.o
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
@ -51,22 +50,22 @@ if HAVE_PIRQ_TABLE object irq_tables.o end
## Romcc output
##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
depends "./failover.E ./romcc"
action "./romcc -O -mcpu=c3 -o failover.inc --label-prefix=failover ./failover.E"
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "./auto.E ./romcc"
action "./romcc -O -mcpu=c3 ./auto.E "
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
##
@ -97,11 +96,6 @@ mainboardinit arch/i386/lib/cpu_reset.inc
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
##
## Setup our mtrrs
##
# mainboardinit cpu/p6/earlymtrr.inc
###
### This is the early phase of linuxBIOS startup
### Things are delicate and we test to see if we should
@ -119,7 +113,10 @@ end
##
## Setup RAM
##
mainboardinit cpu/x86/fpu/enable_fpu.inc
mainboardinit cpu/x86/mmx/enable_mmx.inc
mainboardinit ./auto.inc
mainboardinit cpu/x86/mmx/disable_mmx.inc
##
## Include the secondary Configuration files
@ -183,13 +180,6 @@ chip northbridge/via/vt8601
end
end
end
chip cpu/via/model_centaur
chip cpu/via/model_centaur
end
end
##
## Include the old serial code for those few places that still need it.
##
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc

13
src/mainboard/via/epia/auto.c
View File

@ -2,7 +2,9 @@
#include <stdint.h>
#include <device/pci_def.h>
#if 0
#include <cpu/x86/lapic.h>
#endif
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
@ -12,6 +14,7 @@
#include "ram/ramtest.c"
#include "northbridge/via/vt8601/raminit.h"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
/*
*/
@ -93,14 +96,19 @@ static void enable_shadow_ram(void)
pci_write_config8(dev, 0x63, shadowreg);
}
static void main(void)
static void main(unsigned long bist)
{
unsigned long x;
if (bist == 0) {
early_mtrr_init();
}
enable_vt8231_serial();
uart_init();
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
enable_mainboard_devices();
enable_smbus();
@ -134,5 +142,4 @@ static void main(void)
ram_check(check_addrs[i].lo, check_addrs[i].hi);
}
#endif
early_mtrr_init();
}

37
src/mainboard/via/epia/failover.c
View File

@ -5,25 +5,28 @@
#include <arch/io.h>
#include "arch/romcc_io.h"
#include "pc80/mc146818rtc_early.c"
#include "cpu/x86/lapic/boot_cpu.c"
static void main(void)
static unsigned long main(unsigned long bist)
{
/* for now, just always assume failure */
#if 0
/* Is this a cpu reset? */
if (cpu_init_detected()) {
if (last_boot_normal()) {
asm("jmp __normal_image");
} else {
asm("jmp __cpu_reset");
}
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
asm("jmp __normal_image");
if (do_normal_boot()) {
goto normal_image;
}
#endif
else {
goto fallback_image;
}
normal_image:
asm volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
: /* clobbers */
);
cpu_reset:
asm volatile ("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
: /* clobbers */
);
fallback_image:
return bist;
}

28
src/mainboard/via/epia/mainboard.c
View File

@ -3,36 +3,10 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <arch/io.h>
#include "chip.h"
static unsigned int
mainboard_scan_bus(device_t root, unsigned int maxbus)
{
int retval;
printk_spew("%s: root %p maxbus %d\n", __FUNCTION__, root, maxbus);
retval = pci_scan_bus(root->bus, 0, 0xff, maxbus);
printk_spew("DONE %s: return %d\n", __FUNCTION__, maxbus);
return maxbus;
}
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = root_dev_enable_resources,
.init = root_dev_init,
.scan_bus = mainboard_scan_bus,
.enable = 0,
};
static void enable_dev(device_t dev)
{
dev->ops = &mainboard_operations;
}
struct chip_operations mainboard_via_epia_ops = {
.enable_dev = enable_dev,
.name = "VIA EPIA mainboard ",
CHIP_NAME("VIA EPIA mainboard ")
};

2
src/northbridge/amd/amdk8/northbridge.c
View File

@ -717,6 +717,7 @@ static void enable_dev(struct device *dev)
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
dev->ops = &pci_domain_ops;
pci_set_method_conf1();
}
else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
dev->ops = &cpu_bus_ops;
@ -724,5 +725,6 @@ static void enable_dev(struct device *dev)
}
struct chip_operations northbridge_amd_amdk8_ops = {
CHIP_NAME("AMD K8 Northbridge")
.enable_dev = enable_dev,
};

122
src/northbridge/emulation/qemu-i386/northbridge.c
View File

@ -3,82 +3,75 @@
#include <stdint.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/hypertransport.h>
#include <stdlib.h>
#include <string.h>
#include <bitops.h>
#include "chip.h"
#include "northbridge.h"
void hard_reset(void)
{
printk_err("Hard_RESET!!!\n");
}
#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
static void pci_domain_read_resources(device_t dev)
{
struct resource *resource;
unsigned reg;
struct resource *resource;
/* Initialize the system wide io space constraints */
resource = new_resource(dev, 0);
resource->base = 0x400;
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO;
compute_allocate_resource(&dev->link[0], resource,
IORESOURCE_IO, IORESOURCE_IO);
/* Initialize the system wide io space constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, 1);
resource->limit = 0xffffffffULL;
resource->flags = IORESOURCE_MEM;
compute_allocate_resource(&dev->link[0], resource,
IORESOURCE_MEM, IORESOURCE_MEM);
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
resource->limit = 0xffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
}
static void ram_resource(device_t dev, unsigned long index,
unsigned long basek, unsigned long sizek)
unsigned long basek, unsigned long sizek)
{
struct resource *resource;
struct resource *resource;
if (!sizek) {
return;
}
resource = new_resource(dev, index);
resource->base = ((resource_t)basek) << 10;
resource->size = ((resource_t)sizek) << 10;
resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
if (!sizek) {
return;
}
resource = new_resource(dev, index);
resource->base = ((resource_t)basek) << 10;
resource->size = ((resource_t)sizek) << 10;
resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
static void tolm_test(void *gp, struct device *dev, struct resource *new)
{
struct resource **best_p = gp;
struct resource *best;
best = *best_p;
if (!best || (best->base > new->base)) {
best = new;
}
*best_p = best;
}
static uint32_t find_pci_tolm(struct bus *bus)
{
struct resource *min;
uint32_t tolm;
min = 0;
search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
tolm = 0xffffffffUL;
if (min && tolm > min->base) {
tolm = min->base;
}
return tolm;
}
static void pci_domain_set_resources(device_t dev)
{
struct resource *resource, *last;
device_t mc_dev;
uint32_t pci_tolm;
uint32_t pci_tolm;
uint32_t idx;
pci_tolm = 0xffffffffUL;
last = &dev->resource[dev->resources];
for(resource = &dev->resource[0]; resource < last; resource++)
{
compute_allocate_resource(&dev->link[0], resource,
BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK);
resource->flags |= IORESOURCE_STORED;
report_resource_stored(dev, resource, "");
if ((resource->flags & IORESOURCE_MEM) &&
(pci_tolm > resource->base))
{
pci_tolm = resource->base;
}
}
pci_tolm = find_pci_tolm(&dev->link[0]);
mc_dev = dev->link[0].children;
if (mc_dev) {
unsigned long tomk, tolmk;
@ -105,29 +98,28 @@ static void pci_domain_set_resources(device_t dev)
static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
{
max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
return max;
max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
return max;
}
static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources,
.enable_resources = enable_childrens_resources,
.init = 0,
.scan_bus = pci_domain_scan_bus,
.read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources,
.enable_resources = enable_childrens_resources,
.init = 0,
.scan_bus = pci_domain_scan_bus,
};
static void enable_dev(struct device *dev)
{
struct device_path path;
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
dev->ops = &pci_domain_ops;
}
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
dev->ops = &pci_domain_ops;
pci_set_method();
}
}
struct chip_operations northbridge_emulation_qemu_i386_ops = {
// .name = "QEMU Northbridge",
CHIP_NAME("QEMU Northbridge")
.enable_dev = enable_dev,
};

59
src/northbridge/intel/e7501/northbridge.c
View File

@ -16,19 +16,14 @@ static void pci_domain_read_resources(device_t dev)
unsigned reg;
/* Initialize the system wide io space constraints */
resource = new_resource(dev, 0);
resource->base = 0x400;
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO;
compute_allocate_resource(&dev->link[0], resource,
IORESOURCE_IO, IORESOURCE_IO);
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, 1);
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
resource->limit = 0xffffffffULL;
resource->flags = IORESOURCE_MEM;
compute_allocate_resource(&dev->link[0], resource,
IORESOURCE_MEM, IORESOURCE_MEM);
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
}
static void ram_resource(device_t dev, unsigned long index,
@ -46,29 +41,37 @@ static void ram_resource(device_t dev, unsigned long index,
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
static void tolm_test(void *gp, struct device *dev, struct resource *new)
{
struct resource **best_p = gp;
struct resource *best;
best = *best_p;
if (!best || (best->base > new->base)) {
best = new;
}
*best_p = best;
}
static uint32_t find_pci_tolm(struct bus *bus)
{
struct resource *min;
uint32_t tolm;
min = 0;
search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
tolm = 0xffffffffUL;
if (min && tolm > min->base) {
tolm = min->base;
}
return tolm;
}
static void pci_domain_set_resources(device_t dev)
{
struct resource *resource, *last;
device_t mc_dev;
uint32_t pci_tolm;
pci_tolm = 0xffffffffUL;
last = &dev->resource[dev->resources];
for(resource = &dev->resource[0]; resource < last; resource++)
{
compute_allocate_resource(&dev->link[0], resource,
BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK);
resource->flags |= IORESOURCE_STORED;
report_resource_stored(dev, resource, "");
if ((resource->flags & IORESOURCE_MEM) &&
(pci_tolm > resource->base))
{
pci_tolm = resource->base;
}
}
pci_tolm = find_pci_tolm(&dev->link[0]);
mc_dev = dev->link[0].children;
if (mc_dev) {
/* Figure out which areas are/should be occupied by RAM.
@ -175,16 +178,16 @@ static struct device_operations cpu_bus_ops = {
static void enable_dev(struct device *dev)
{
struct device_path path;
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
dev->ops = &pci_domain_ops;
pci_set_method_conf1();
}
else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
dev->ops = &cpu_bus_ops;
}
}
struct chip_operations northbridge_intel_e7501_ops = {
CHIP_NAME("Intel E7501 northbridge")
.enable_dev = enable_dev,
};

59
src/northbridge/intel/i855pm/northbridge.c
View File

@ -16,19 +16,14 @@ static void pci_domain_read_resources(device_t dev)
unsigned reg;
/* Initialize the system wide io space constraints */
resource = new_resource(dev, 0);
resource->base = 0x400;
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO;
compute_allocate_resource(&dev->link[0], resource,
IORESOURCE_IO, IORESOURCE_IO);
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, 1);
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
resource->limit = 0xffffffffULL;
resource->flags = IORESOURCE_MEM;
compute_allocate_resource(&dev->link[0], resource,
IORESOURCE_MEM, IORESOURCE_MEM);
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
}
static void ram_resource(device_t dev, unsigned long index,
@ -46,29 +41,36 @@ static void ram_resource(device_t dev, unsigned long index,
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
static void tolm_test(void *gp, struct device *dev, struct resource *new)
{
struct resource **best_p = gp;
struct resource *best;
best = *best_p;
if (!best || (best->base > new->base)) {
best = new;
}
*best_p = best;
}
static uint32_t find_pci_tolm(struct bus *bus)
{
struct resource *min;
uint32_t tolm;
min = 0;
search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
tolm = 0xffffffffUL;
if (min && tolm > min->base) {
tolm = min->base;
}
return tolm;
}
static void pci_domain_set_resources(device_t dev)
{
struct resource *resource, *last;
device_t mc_dev;
uint32_t pci_tolm;
pci_tolm = 0xffffffffUL;
last = &dev->resource[dev->resources];
for(resource = &dev->resource[0]; resource < last; resource++)
{
compute_allocate_resource(&dev->link[0], resource,
BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK);
resource->flags |= IORESOURCE_STORED;
report_resource_stored(dev, resource, "");
if ((resource->flags & IORESOURCE_MEM) &&
(pci_tolm > resource->base))
{
pci_tolm = resource->base;
}
}
pci_tolm = find_pci_tolm(&dev->link[0]);
mc_dev = dev->link[0].children;
if (mc_dev) {
/* Figure out which areas are/should be occupied by RAM.
@ -147,6 +149,7 @@ static void enable_dev(struct device *dev)
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
dev->ops = &pci_domain_ops;
pci_set_method();
}
else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
dev->ops = &cpu_bus_ops;
@ -154,6 +157,6 @@ static void enable_dev(struct device *dev)
}
struct chip_operations northbridge_intel_i855pm_control = {
.name = "intel i855pm Northbridge",
CHIP_NAME("intel i855pm Northbridge")
.enable_dev = enable_dev,
};

1
src/northbridge/intel/i855pm/raminit.c
View File

@ -19,6 +19,7 @@
/* converted to C 6/2004 yhlu */
#define DEBUG_RAM_CONFIG 1
#undef ASM_CONSOLE_LOGLEVEL
#define ASM_CONSOLE_LOGLEVEL 9
#define dumpnorth() dump_pci_device(PCI_DEV(0, 0, 1))

58
src/northbridge/transmeta/tm5800/northbridge.c
View File

@ -19,19 +19,14 @@ static void pci_domain_read_resources(device_t dev)
unsigned reg;
/* Initialize the system wide io space constraints */
resource = new_resource(dev, 0);
resource->base = 0x400;
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO;
compute_allocate_resource(&dev->link[0], resource,
IORESOURCE_IO, IORESOURCE_IO);
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, 1);
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
resource->limit = 0xffffffffULL;
resource->flags = IORESOURCE_MEM;
compute_allocate_resource(&dev->link[0], resource,
IORESOURCE_MEM, IORESOURCE_MEM);
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
}
static void ram_resource(device_t dev, unsigned long index,
@ -49,29 +44,37 @@ static void ram_resource(device_t dev, unsigned long index,
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
static void tolm_test(void *gp, struct device *dev, struct resource *new)
{
struct resource **best_p = gp;
struct resource *best;
best = *best_p;
if (!best || (best->base > new->base)) {
best = new;
}
*best_p = best;
}
static uint32_t find_pci_tolm(struct bus *bus)
{
struct resource *min;
uint32_t tolm;
min = 0;
search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
tolm = 0xffffffffUL;
if (min && tolm > min->base) {
tolm = min->base;
}
return tolm;
}
static void pci_domain_set_resources(device_t dev)
{
struct resource *resource, *last;
device_t mc_dev;
uint32_t pci_tolm;
pci_tolm = 0xffffffffUL;
last = &dev->resource[dev->resources];
for(resource = &dev->resource[0]; resource < last; resource++)
{
compute_allocate_resource(&dev->link[0], resource,
BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK);
resource->flags |= IORESOURCE_STORED;
report_resource_stored(dev, resource, "");
if ((resource->flags & IORESOURCE_MEM) &&
(pci_tolm > resource->base))
{
pci_tolm = resource->base;
}
}
pci_tolm = find_pci_tolm(&dev->link[0]);
mc_dev = dev->link[0].children;
if (mc_dev) {
/* Figure out which areas are/should be occupied by RAM.
@ -139,6 +142,7 @@ static void enable_dev(struct device *dev)
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
dev->ops = &pci_domain_ops;
pci_set_method();
}
else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
dev->ops = &cpu_bus_ops;
@ -146,6 +150,6 @@ static void enable_dev(struct device *dev)
}
struct chip_operations northbridge_transmeta_tm5800_control = {
.name = "Transmeta tm5800 Northbridge",
CHIP_NAME("Transmeta tm5800 Northbridge")
.enable_dev = enable_dev,
};

63
src/northbridge/via/vt8601/northbridge.c
View File

@ -55,19 +55,14 @@ static void pci_domain_read_resources(device_t dev)
struct resource *resource;
/* Initialize the system wide io space constraints */
resource = new_resource(dev, 0);
resource->base = 0x400;
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO;
compute_allocate_resource(&dev->link[0], resource,
IORESOURCE_IO, IORESOURCE_IO);
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, 1);
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
resource->limit = 0xffffffffULL;
resource->flags = IORESOURCE_MEM;
compute_allocate_resource(&dev->link[0], resource,
IORESOURCE_MEM, IORESOURCE_MEM);
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
}
static void ram_resource(device_t dev, unsigned long index,
@ -85,32 +80,39 @@ static void ram_resource(device_t dev, unsigned long index,
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
static const uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
0x56, 0x57};
static void tolm_test(void *gp, struct device *dev, struct resource *new)
{
struct resource **best_p = gp;
struct resource *best;
best = *best_p;
if (!best || (best->base > new->base)) {
best = new;
}
*best_p = best;
}
static uint32_t find_pci_tolm(struct bus *bus)
{
struct resource *min;
uint32_t tolm;
min = 0;
search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
tolm = 0xffffffffUL;
if (min && tolm > min->base) {
tolm = min->base;
}
return tolm;
}
static void pci_domain_set_resources(device_t dev)
{
struct resource *resource, *last;
static const uint8_t ramregs[] = {
0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57
};
device_t mc_dev;
uint32_t pci_tolm;
pci_tolm = 0xffffffffUL;
last = &dev->resource[dev->resources];
for(resource = &dev->resource[0]; resource < last; resource++)
{
compute_allocate_resource(&dev->link[0], resource,
BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK);
resource->flags |= IORESOURCE_STORED;
report_resource_stored(dev, resource, "");
if ((resource->flags & IORESOURCE_MEM) &&
(pci_tolm > resource->base))
{
pci_tolm = resource->base;
}
}
pci_tolm = find_pci_tolm(&dev->link[0]);
mc_dev = dev->link[0].children;
if (mc_dev) {
unsigned long tomk, tolmk;
@ -184,6 +186,7 @@ static void enable_dev(struct device *dev)
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
dev->ops = &pci_domain_ops;
pci_set_method();
}
else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
dev->ops = &cpu_bus_ops;
@ -191,6 +194,6 @@ static void enable_dev(struct device *dev)
}
struct chip_operations northbridge_via_vt8601_ops = {
CHIP_NAME("VIA vt8601 Northbridge")
.enable_dev = enable_dev,
.name = "VIA vt8601 Northbridge",
};

59
src/northbridge/via/vt8623/northbridge.c
View File

@ -135,19 +135,14 @@ static void pci_domain_read_resources(device_t dev)
unsigned reg;
/* Initialize the system wide io space constraints */
resource = new_resource(dev, 0);
resource->base = 0x400;
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO;
compute_allocate_resource(&dev->link[0], resource,
IORESOURCE_IO, IORESOURCE_IO);
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, 1);
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
resource->limit = 0xffffffffULL;
resource->flags = IORESOURCE_MEM;
compute_allocate_resource(&dev->link[0], resource,
IORESOURCE_MEM, IORESOURCE_MEM);
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
}
static void ram_resource(device_t dev, unsigned long index,
@ -165,31 +160,38 @@ static void ram_resource(device_t dev, unsigned long index,
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
static const uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d };
static void tolm_test(void *gp, struct device *dev, struct resource *new)
{
struct resource **best_p = gp;
struct resource *best;
best = *best_p;
if (!best || (best->base > new->base)) {
best = new;
}
*best_p = best;
}
static uint32_t find_pci_tolm(struct bus *bus)
{
struct resource *min;
uint32_t tolm;
min = 0;
search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
tolm = 0xffffffffUL;
if (min && tolm > min->base) {
tolm = min->base;
}
return tolm;
}
static void pci_domain_set_resources(device_t dev)
{
static const uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d };
struct resource *resource, *last;
device_t mc_dev;
uint32_t pci_tolm;
pci_tolm = 0xffffffffUL;
last = &dev->resource[dev->resources];
for(resource = &dev->resource[0]; resource < last; resource++)
{
compute_allocate_resource(&dev->link[0], resource,
BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK);
resource->flags |= IORESOURCE_STORED;
report_resource_stored(dev, resource, "");
if ((resource->flags & IORESOURCE_MEM) &&
(pci_tolm > resource->base))
{
pci_tolm = resource->base;
}
}
pci_tolm = find_pci_tolm(&dev->link[0]);
mc_dev = dev->link[0].children;
if (mc_dev) {
unsigned long tomk, tolmk;
@ -266,6 +268,7 @@ static void enable_dev(struct device *dev)
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
dev->ops = &pci_domain_ops;
pci_set_method();
}
else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
dev->ops = &cpu_bus_ops;
@ -273,6 +276,6 @@ static void enable_dev(struct device *dev)
}
struct chip_operations northbridge_via_vt8623_control = {
CHIP_NAME("VIA vt8623 Northbridge")
.enable_dev = enable_dev,
.name = "VIA vt8623 Northbridge",
};

2
src/northbridge/via/vt8623/raminit.c
View File

@ -1,4 +1,4 @@
#include <cpu/p6/mtrr.h>
#include <cpu/x86/mtrr.h>
#include "raminit.h"
/*

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