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libpayload: Remove PC Keyboard from ARM build 

The keyboard.c uses IO cycles to access the legacy PC keyboard device.
ARM can't do IO cycles, so remove the option for ARM configs.

Change-Id: Ifc6c2368563f27867f4babad5afdde0e78f4cf78
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7922
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Marc Jones 2014-12-23 15:22:30 -07:00
parent 86127c7bfe
commit 019bacb41a
2 changed files with 4 additions and 7 deletions
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3
payloads/libpayload/Config.in
View File

@ -237,7 +237,8 @@ config COREBOOT_VIDEO_CONSOLE
config PC_KEYBOARD config PC_KEYBOARD
bool "Allow input from a PC keyboard" bool "Allow input from a PC keyboard"
default y default y if ARCH_X86 # uses IO
default n
config PC_KEYBOARD_LAYOUT_US config PC_KEYBOARD_LAYOUT_US
bool "English (US) keyboard layout" bool "English (US) keyboard layout"

8
payloads/libpayload/configs/defconfig-arm
View File

@ -1,7 +1,7 @@
# #
# Automatically generated make config: don't edit # Automatically generated make config: don't edit
# libpayload version: 0.2.0 # libpayload version: 0.2.0
# Wed Nov 12 14:57:03 2014 # Tue Dec 23 15:19:30 2014
# #
# #
@ -42,9 +42,7 @@ CONFIG_LP_SERIAL_CONSOLE=y
# CONFIG_LP_SERIAL_ACS_FALLBACK is not set # CONFIG_LP_SERIAL_ACS_FALLBACK is not set
CONFIG_LP_VIDEO_CONSOLE=y CONFIG_LP_VIDEO_CONSOLE=y
# CONFIG_LP_COREBOOT_VIDEO_CONSOLE is not set # CONFIG_LP_COREBOOT_VIDEO_CONSOLE is not set
CONFIG_LP_PC_KEYBOARD=y # CONFIG_LP_PC_KEYBOARD is not set
CONFIG_LP_PC_KEYBOARD_LAYOUT_US=y
# CONFIG_LP_PC_KEYBOARD_LAYOUT_DE is not set
# #
# Drivers # Drivers
@ -70,5 +68,3 @@ CONFIG_LP_USB_GEN_HUB=y
CONFIG_LP_LITTLE_ENDIAN=y CONFIG_LP_LITTLE_ENDIAN=y
# CONFIG_LP_IO_ADDRESS_SPACE is not set # CONFIG_LP_IO_ADDRESS_SPACE is not set
CONFIG_LP_ARCH_SPECIFIC_OPTIONS=y CONFIG_LP_ARCH_SPECIFIC_OPTIONS=y
CONFIG_LP_COREBOOT_INFO_RANGE_BASE=0x10
CONFIG_LP_COREBOOT_INFO_RANGE_SIZE=0x4000000