diff --git a/src/mainboard/facebook/watson/Kconfig b/src/mainboard/facebook/watson/Kconfig
index 2ebc0206cf..919117d653 100644
--- a/src/mainboard/facebook/watson/Kconfig
+++ b/src/mainboard/facebook/watson/Kconfig
@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select HAVE_ACPI_TABLES
 	select HAVE_OPTION_TABLE
 	select INTEGRATED_UART
+	select IPMI_KCS if BOARD_FACEBOOK_WATSON_V2
 	select SERIRQ_CONTINUOUS_MODE
 	select MAINBOARD_USES_IFD_GBE_REGION
 	select MAINBOARD_HAS_LPC_TPM
diff --git a/src/mainboard/facebook/watson/include/variants.h b/src/mainboard/facebook/watson/include/variants.h
index 46989168c9..d364b8b007 100644
--- a/src/mainboard/facebook/watson/include/variants.h
+++ b/src/mainboard/facebook/watson/include/variants.h
@@ -21,5 +21,6 @@
 #include <soc/romstage.h>
 
 void variant_romstage_fsp_init_params(UPD_DATA_REGION *UpdData);
+void variant_early_mainboard_romstage_entry(void);
 
 #endif /* BASEBOARD_VARIANTS_H */
diff --git a/src/mainboard/facebook/watson/romstage.c b/src/mainboard/facebook/watson/romstage.c
index b8df798031..d65ac0ef51 100644
--- a/src/mainboard/facebook/watson/romstage.c
+++ b/src/mainboard/facebook/watson/romstage.c
@@ -25,7 +25,7 @@
  */
 void early_mainboard_romstage_entry(void)
 {
-
+	variant_early_mainboard_romstage_entry();
 }
 
 /**
@@ -52,3 +52,8 @@ __weak void variant_romstage_fsp_init_params(UPD_DATA_REGION *UpdData)
 {
 
 }
+
+__weak void variant_early_mainboard_romstage_entry(void)
+{
+
+}
diff --git a/src/mainboard/facebook/watson/variants/watson_v2/romstage.c b/src/mainboard/facebook/watson/variants/watson_v2/romstage.c
index 55f30255e8..2e571b9713 100644
--- a/src/mainboard/facebook/watson/variants/watson_v2/romstage.c
+++ b/src/mainboard/facebook/watson/variants/watson_v2/romstage.c
@@ -15,6 +15,9 @@
  * GNU General Public License for more details.
  */
 
+#include <device/pci_ops.h>
+#include <soc/lpc.h>
+#include <soc/pci_devs.h>
 #include <soc/romstage.h>
 #include <variants.h>
 
@@ -46,3 +49,12 @@ void variant_romstage_fsp_init_params(UPD_DATA_REGION *UpdData)
 	UpdData->HotPlug_PchPciPort7 = 1;
 	UpdData->HotPlug_PchPciPort8 = 1;
 }
+
+void variant_early_mainboard_romstage_entry(void)
+{
+	// Enable LPC IO ports 0xca2, 0xca8 for IPMI
+	pci_write_config32(PCH_DEV_LPC, LPC_GEN2_DEC,
+		(0 << 16) | ALIGN_DOWN(0xca2, 4) | 1);
+	pci_write_config32(PCH_DEV_LPC, LPC_GEN3_DEC,
+		(0 << 16) | ALIGN_DOWN(0xca8, 4) | 1);
+}