From 01a9c1bf77486bf197e6cd65d3d6c12973d14899 Mon Sep 17 00:00:00 2001 From: Corey Osgood Date: Fri, 17 Oct 2008 02:34:06 +0000 Subject: [PATCH] Final fix for C7 boards, which are still using ROMCC, to be able to build. As far as I know, no C7 boards currently in the tree use SPI flash. Signed-off-by: Corey Osgood Acked-by: Peter Stuge git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3665 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/via/vt8237r/vt8237r_early_smbus.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/southbridge/via/vt8237r/vt8237r_early_smbus.c b/src/southbridge/via/vt8237r/vt8237r_early_smbus.c index af91707ec9..7b85a1979a 100644 --- a/src/southbridge/via/vt8237r/vt8237r_early_smbus.c +++ b/src/southbridge/via/vt8237r/vt8237r_early_smbus.c @@ -336,6 +336,7 @@ void enable_rom_decode(void) pci_write_config8(dev, 0x41, 0x7f); } +#if defined(__GNUC__) void vt8237_early_spi_init(void) { device_t dev; @@ -358,6 +359,7 @@ void vt8237_early_spi_init(void) spireg = (u16 *) (VT8237S_SPI_MEM_BASE + 0x6c); (*spireg) &= 0xff00; } +#endif /* This #if is special. ROMCC chokes on the (rom == NULL) comparison. * Since the whole function is only called for one target and that target