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Snow: correctly disable trust zone hardware 

The kernel assumes that trust zone is disabled.

Change-Id: Ia8d6fa69adcb812a747d8b89eb77e57144423eaa
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/64722
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-on: http://review.coreboot.org/4431
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Ronald G. Minnich 2013-08-05 17:18:44 -07:00 committed by Patrick Georgi
parent b0efbd3910
commit 01b438367c
2 changed files with 76 additions and 0 deletions
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25
src/cpu/samsung/exynos5250/cpu.c
View File

@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright 2013 Google Inc.
* Copyright (C) 2012 Samsung Electronics
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -35,6 +36,28 @@
static unsigned int cpu_id;
static unsigned int cpu_rev;
/* Setting TZPC[TrustZone Protection Controller] */
static void tzpc_init(void)
{
struct exynos_tzpc *tzpc;
unsigned int addr;
for (addr = TZPC0_BASE; addr <= TZPC9_BASE; addr += TZPC_BASE_OFFSET) {
tzpc = (struct exynos_tzpc *)addr;
if (addr == TZPC0_BASE)
writel(R0SIZE, &tzpc->r0size);
writel(DECPROTXSET, &tzpc->decprot0set);
writel(DECPROTXSET, &tzpc->decprot1set);
if (addr != TZPC9_BASE) {
writel(DECPROTXSET, &tzpc->decprot2set);
writel(DECPROTXSET, &tzpc->decprot3set);
}
}
}
static void set_cpu_id(void)
{
cpu_id = readl((void *)EXYNOS_PRO_ID);
@ -122,6 +145,8 @@ static void cpu_enable(device_t dev)
exynos_displayport_init(dev, lcdbase, fb_size);
set_cpu_id();
tzpc_init();
}
static void cpu_init(device_t dev)

51
src/cpu/samsung/exynos5250/cpu.h
View File

@ -91,6 +91,31 @@
/* Distance between each Trust Zone PC register set */
#define TZPC_BASE_OFFSET 0x10000
/* TZPC : Register Offsets */
#define TZPC0_BASE 0x10100000
#define TZPC1_BASE 0x10110000
#define TZPC2_BASE 0x10120000
#define TZPC3_BASE 0x10130000
#define TZPC4_BASE 0x10140000
#define TZPC5_BASE 0x10150000
#define TZPC6_BASE 0x10160000
#define TZPC7_BASE 0x10170000
#define TZPC8_BASE 0x10180000
#define TZPC9_BASE 0x10190000
#define TZPC10_BASE 0x100E0000
#define TZPC11_BASE 0x100F0000
/*
* TZPC Register Value :
* R0SIZE: 0x0 : Size of secured ram
*/
#define R0SIZE 0x0
/*
* TZPC Decode Protection Register Value :
* DECPROTXSET: 0xFF : Set Decode region to non-secure
*/
#define DECPROTXSET 0xFF
#define samsung_get_base_adc() ((struct exynos5_adc *)EXYNOS5_ADC_BASE)
#define samsung_get_base_clock() ((struct exynos5_clock *)EXYNOS5_CLOCK_BASE)
@ -130,6 +155,32 @@ extern struct tmu_info exynos5250_tmu_info;
#define RAM_BASE_KB (CONFIG_SYS_SDRAM_BASE >> 10)
#define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL)
struct exynos_tzpc {
u32 r0size;
u8 res1[0x7FC];
u32 decprot0stat;
u32 decprot0set;
u32 decprot0clr;
u32 decprot1stat;
u32 decprot1set;
u32 decprot1clr;
u32 decprot2stat;
u32 decprot2set;
u32 decprot2clr;
u32 decprot3stat;
u32 decprot3set;
u32 decprot3clr;
u8 res2[0x7B0];
u32 periphid0;
u32 periphid1;
u32 periphid2;
u32 periphid3;
u32 pcellid0;
u32 pcellid1;
u32 pcellid2;
u32 pcellid3;
};
static inline u32 get_fb_base_kb(void)
{
return RAM_BASE_KB + RAM_SIZE_KB - FB_SIZE_KB;