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soc/intel/fsp_baytrail: Drop some __BOOTBLOCK__ guards 

Change in ssus_disable_internal_pull() is for romcc
compatibility.

Change-Id: Ib72a669a3b5cd90e74d917f74f35453a85941658
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Kyösti Mälkki 2019-09-25 15:22:42 +03:00
parent 3356305ca6
commit 01b60633a8
1 changed files with 6 additions and 9 deletions
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15
src/soc/intel/fsp_baytrail/include/soc/gpio.h
View File

@ -313,8 +313,6 @@
#define GPSSUS_GPIO_F1_RANGE_START 11
#define GPSSUS_GPIO_F1_RANGE_END 21
#ifndef __BOOTBLOCK__
struct soc_gpio_map {
u32 pad_conf0;
u32 pad_conf1;
@ -360,8 +358,6 @@ void write_ssus_gpio(uint8_t gpio_num, uint8_t val);
void configure_ssus_gpio(uint8_t gpio_num, uint32_t pconf0, uint32_t pad_val);
void configure_score_gpio(uint8_t gpio_num, uint32_t pconf0, uint32_t pad_val);
#endif /* #ifndef __BOOTBLOCK__ */
/* Functions / defines for changing GPIOs in romstage */
/* SCORE Pad definitions. */
#define UART_RXD_PAD 82
@ -401,7 +397,6 @@ static inline void ssus_select_func(int pad, int func)
write32(pconf0_addr, reg);
}
#ifndef __BOOTBLOCK__
/* These functions require that the input pad be configured as an input GPIO */
static inline int score_get_gpio(int pad)
@ -436,10 +431,12 @@ static inline void ssus_set_gpio(int pad, int val)
static inline void ssus_disable_internal_pull(int pad)
{
const uint32_t pull_mask = ~(0xf << 7);
write32(ssus_pconf0(pad), read32(ssus_pconf0(pad)) & pull_mask);
uint32_t reg;
uint32_t *pconf0_addr = ssus_pconf0(pad);
reg = read32(pconf0_addr);
reg &= ~(0xf << 7);
write32(pconf0_addr, reg);
}
#endif /* #ifndef __BOOTBLOCK__ */
#endif /* _BAYTRAIL_GPIO_H_ */