vendorcode/amd/pi/00670F00/Proc/Fch/Common: Remove VENDORCODE_FULL_SUPPORT

Remove VENDORCODE_FULL_SUPPORT from files FchLib.c and FchPeLib.c.

BUG=b:112578491
TEST=none, VENDORCODE_FULL_SUPPORT already not used.

Change-Id: If24eb7f005720a62a1280fe78ddb54c9d2690150
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Richard Spiegel 2018-08-14 08:16:27 -07:00 committed by Martin Roth
parent e4d46689b3
commit 01b6ea4126
2 changed files with 0 additions and 915 deletions

View File

@ -77,535 +77,3 @@ FchStall (
}
}
#if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT)
/**< cimFchStall - Reserved */
VOID
CimFchStall (
IN UINT32 uSec,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT16 timerAddr;
UINT32 startTime;
UINT32 elapsedTime;
LibAmdMemRead (AccessWidth16, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG64), &timerAddr, StdHeader);
if ( timerAddr == 0 ) {
uSec = uSec / 2;
while ( uSec != 0 ) {
LibAmdIoRead (AccessWidth8, FCHOEM_IO_DELAY_PORT, (UINT8*)&elapsedTime, StdHeader);
uSec--;
}
} else {
LibAmdIoRead (AccessWidth32, timerAddr, &startTime, StdHeader);
for ( ;; ) {
LibAmdIoRead (AccessWidth32, timerAddr, &elapsedTime, StdHeader);
if ( elapsedTime < startTime ) {
elapsedTime = elapsedTime + FCH_MAX_TIMER - startTime;
} else {
elapsedTime = elapsedTime - startTime;
}
if ( (elapsedTime * FCHOEM_ELAPSED_TIME_UNIT / FCHOEM_ELAPSED_TIME_DIVIDER) > uSec ) {
break;
}
}
}
}
/**< FchReset - Reserved */
VOID
FchPciReset (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 PciRstValue;
PciRstValue = 0x06;
LibAmdIoWrite (AccessWidth8, FCH_PCIRST_BASE_IO, &PciRstValue, StdHeader);
}
/**< outPort80 - Reserved */
VOID
OutPort80 (
IN UINT32 pcode,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
LibAmdIoWrite (AccessWidth8, FCHOEM_OUTPUT_DEBUG_PORT, &pcode, StdHeader);
return;
}
/**< outPort1080 - Reserved */
VOID
OutPort1080 (
IN UINT32 pcode,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
LibAmdIoWrite (AccessWidth32, 0x1080, &pcode, StdHeader);
return;
}
/**< FchCopyMem - Reserved */
VOID
FchCopyMem (
IN VOID* pDest,
IN VOID* pSource,
IN UINTN Length
)
{
UINTN i;
UINT8 *Ptr;
UINT8 *Source;
Ptr = (UINT8*)pDest;
Source = (UINT8*)pSource;
for (i = 0; i < Length; i++) {
*Ptr = *Source;
Source++;
Ptr++;
}
}
/** GetRomSigPtr - Reserved **/
VOID*
GetRomSigPtr (
IN UINTN *RomSigPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 RomPtr;
UINT32 RomSig;
UINT16 MswAddr;
*RomSigPtr = 0;
MswAddr = 0xFF00;
do {
RomPtr = (MswAddr << 16) + FCH_ROMSIG_BASE_IO;
LibAmdMemRead (AccessWidth32, (UINT64) RomPtr, &RomSig, StdHeader);
if (RomSig == FCH_ROMSIG_SIGNATURE) {
*RomSigPtr = RomPtr;
break;
}
MswAddr >>= 1;
MswAddr |= BIT15;
} while (MswAddr != 0xFFF8);
return RomSigPtr;
}
/** ReadXhci0Phy - Reserved **/
VOID
ReadXhci0Phy (
IN UINT32 Port,
IN UINT32 Address,
IN UINT32 *Value,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 RegIndex;
UINT32 RegValue;
PCI_ADDR PciAddress;
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + Address, StdHeader);
RegIndex = FCH_XHCI_IND60_REG04;
PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x48;
LibAmdPciWrite (AccessWidth32, PciAddress, &RegIndex, StdHeader);
PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x4C;
LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader);
(*Value) = ( RegValue >> (Port * 8)) & 0x000000FF;
}
/** ReadXhci1Phy - Reserved **/
VOID
ReadXhci1Phy (
IN UINT32 Port,
IN UINT32 Address,
IN UINT32 *Value,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 RegIndex;
UINT32 RegValue;
PCI_ADDR PciAddress;
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + Address, StdHeader);
RegIndex = FCH_XHCI_IND60_REG04;
PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x48;
LibAmdPciWrite (AccessWidth32, PciAddress, &RegIndex, StdHeader);
PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x4C;
LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader);
(*Value) = ( RegValue >> (Port * 8)) & 0x000000FF;
}
/** AcLossControl - Reserved **/
VOID
AcLossControl (
IN UINT8 AcLossControlValue
)
{
AcLossControlValue &= 0x03;
AcLossControlValue |= BIT2;
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5B, AccessWidth8, 0xF0, AcLossControlValue);
}
/** RecordFchConfigPtr - Reserved **/
VOID
RecordFchConfigPtr (
IN UINT32 FchConfigPtr
)
{
RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x08, AccessWidth8, 0, (UINT8) ((FchConfigPtr >> 0) & 0xFF) );
RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x09, AccessWidth8, 0, (UINT8) ((FchConfigPtr >> 8) & 0xFF) );
RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0A, AccessWidth8, 0, (UINT8) ((FchConfigPtr >> 16) & 0xFF) );
RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0B, AccessWidth8, 0, (UINT8) ((FchConfigPtr >> 24) & 0xFF) );
}
/** ReadAlink - Reserved **/
UINT32
ReadAlink (
IN UINT32 Index,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Data;
LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &Index, StdHeader);
LibAmdIoRead (AccessWidth32, ALINK_ACCESS_DATA, &Data, StdHeader);
//Clear Index
Index = 0;
LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &Index, StdHeader);
return Data;
}
/** WriteAlink - Reserved **/
VOID
WriteAlink (
IN UINT32 Index,
IN UINT32 Data,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &Index, StdHeader);
LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_DATA, &Data, StdHeader);
//Clear Index
Index = 0;
LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &Index, StdHeader);
}
/** RwAlink - Reserved **/
VOID
RwAlink (
IN UINT32 Index,
IN UINT32 AndMask,
IN UINT32 OrMask,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 AccessType;
AccessType = Index & 0xE0000000;
if (AccessType == (AXINDC << 29)) {
WriteAlink ((FCH_AX_INDXC_REG30 | AccessType), Index & 0x1FFFFFFF, StdHeader);
Index = FCH_AX_DATAC_REG34 | AccessType;
} else if (AccessType == (AXINDP << 29)) {
WriteAlink ((FCH_AX_INDXP_REG38 | AccessType), Index & 0x1FFFFFFF, StdHeader);
Index = FCH_AX_DATAP_REG3C | AccessType;
}
WriteAlink (Index, (ReadAlink (Index, StdHeader) & AndMask) | OrMask, StdHeader);
}
/*----------------------------------------------------------------------------------------*/
/**
* Read PMIO
*
*
*
* @param[in] Address - PMIO Offset value
* @param[in] OpFlag - Access sizes
* @param[in] Value - Read Data Buffer
* @param[in] StdHeader
*
*/
VOID
ReadPmio (
IN UINT8 Address,
IN UINT8 OpFlag,
IN VOID *Value,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 i;
OpFlag = OpFlag & 0x7f;
OpFlag = 1 << (OpFlag - 1);
for (i = 0; i < OpFlag; i++) {
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD6, &Address, StdHeader);
Address++;
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGCD7, (UINT8 *)Value + i, StdHeader);
}
}
/*----------------------------------------------------------------------------------------*/
/**
* Write PMIO
*
*
*
* @param[in] Address - PMIO Offset value
* @param[in] OpFlag - Access sizes
* @param[in] Value - Write Data Buffer
* @param[in] StdHeader
*
*/
VOID
WritePmio (
IN UINT8 Address,
IN UINT8 OpFlag,
IN VOID *Value,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 i;
OpFlag = OpFlag & 0x7f;
OpFlag = 1 << (OpFlag - 1);
for (i = 0; i < OpFlag; i++) {
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD6, &Address, StdHeader);
Address++;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD7, (UINT8 *)Value + i, StdHeader);
}
}
/*----------------------------------------------------------------------------------------*/
/**
* RwPmio - Read/Write PMIO
*
*
*
* @param[in] Address - PMIO Offset value
* @param[in] OpFlag - Access sizes
* @param[in] AndMask - Data And Mask 32 bits
* @param[in] OrMask - Data OR Mask 32 bits
* @param[in] StdHeader
*
*/
VOID
RwPmio (
IN UINT8 Address,
IN UINT8 OpFlag,
IN UINT32 AndMask,
IN UINT32 OrMask,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Result;
ReadPmio (Address, OpFlag, &Result, StdHeader);
Result = (Result & AndMask) | OrMask;
WritePmio (Address, OpFlag, &Result, StdHeader);
}
/*----------------------------------------------------------------------------------------*/
/**
* Read PMIO2
*
*
*
* @param[in] Address - PMIO2 Offset value
* @param[in] OpFlag - Access sizes
* @param[in] Value - Read Data Buffer
* @param[in] StdHeader
*
*/
VOID
ReadPmio2 (
IN UINT8 Address,
IN UINT8 OpFlag,
IN VOID *Value,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 i;
OpFlag = OpFlag & 0x7f;
OpFlag = 1 << (OpFlag - 1);
for ( i = 0; i < OpFlag; i++ ) {
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD0, &Address, StdHeader);
Address++;
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGCD1, (UINT8 *) Value + i, StdHeader);
}
}
/*----------------------------------------------------------------------------------------*/
/**
* Write PMIO 2
*
*
*
* @param[in] Address - PMIO2 Offset value
* @param[in] OpFlag - Access sizes
* @param[in] Value - Write Data Buffer
* @param[in] StdHeader
*
*/
VOID
WritePmio2 (
IN UINT8 Address,
IN UINT8 OpFlag,
IN VOID *Value,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 i;
OpFlag = OpFlag & 0x7f;
OpFlag = 1 << (OpFlag - 1);
for ( i = 0; i < OpFlag; i++ ) {
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD0, &Address, StdHeader);
Address++;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD1, (UINT8 *) Value + i, StdHeader);
}
}
/*----------------------------------------------------------------------------------------*/
/**
* RwPmio2 - Read/Write PMIO2
*
*
*
* @param[in] Address - PMIO2 Offset value
* @param[in] OpFlag - Access sizes
* @param[in] AndMask - Data And Mask 32 bits
* @param[in] OrMask - Data OR Mask 32 bits
* @param[in] StdHeader
*
*/
VOID
RwPmio2 (
IN UINT8 Address,
IN UINT8 OpFlag,
IN UINT32 AndMask,
IN UINT32 OrMask,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Result;
ReadPmio2 (Address, OpFlag, &Result, StdHeader);
Result = (Result & AndMask) | OrMask;
WritePmio2 (Address, OpFlag, &Result, StdHeader);
}
/*----------------------------------------------------------------------------------------*/
/**
* Read BIOSRAM
*
*
*
* @param[in] Address - BIOSRAM Offset value
* @param[in] OpFlag - Access sizes
* @param[in] Value - Read Data Buffer
* @param[in] StdHeader
*
*/
VOID
ReadBiosram (
IN UINT8 Address,
IN UINT8 OpFlag,
IN VOID *Value,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 i;
OpFlag = OpFlag & 0x7f;
OpFlag = 1 << (OpFlag - 1);
for (i = 0; i < OpFlag; i++) {
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD4, &Address, StdHeader);
Address++;
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGCD5, (UINT8 *)Value + i, StdHeader);
}
}
/*----------------------------------------------------------------------------------------*/
/**
* Write BIOSRAM
*
*
*
* @param[in] Address - BIOSRAM Offset value
* @param[in] OpFlag - Access sizes
* @param[in] Value - Write Data Buffer
* @param[in] StdHeader
*
*/
VOID
WriteBiosram (
IN UINT8 Address,
IN UINT8 OpFlag,
IN VOID *Value,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 i;
OpFlag = OpFlag & 0x7f;
OpFlag = 1 << (OpFlag - 1);
for (i = 0; i < OpFlag; i++) {
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD4, &Address, StdHeader);
Address++;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD5, (UINT8 *)Value + i, StdHeader);
}
}
/*----------------------------------------------------------------------------------------*/
/**
* Record SMI Status
*
*
* @param[in] StdHeader
*
*/
VOID
RecordSmiStatus (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINTN Index;
UINT8 SwSmiValue;
ACPIMMIO8 (0xfed80320) |= 0x01;
for ( Index = 0; Index < 20; Index++ ) {
ACPIMMIO8 (0xfed10020 + Index) = ACPIMMIO8 (0xfed80280 + Index);
}
LibAmdIoRead (AccessWidth8, 0xB0, &SwSmiValue, StdHeader);
ACPIMMIO8 (0xfed10040) = SwSmiValue;
}
/*----------------------------------------------------------------------------------------*/
/**
* Clear All SMI Status
*
*
* @param[in] StdHeader
*
*/
VOID
ClearAllSmiStatus (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINTN Index;
for ( Index = 0; Index < 20; Index++ ) {
ACPIMMIO8 (0xfed80280 + Index) |= 0;
}
}
#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) */

View File

@ -52,93 +52,6 @@
*/
#define FILECODE PROC_FCH_COMMON_FCHPELIB_FILECODE
#if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT)
/*----------------------------------------------------------------------------------------*/
/**
* ProgramFchSciMapTbl - Program FCH SCI Map table (8 bits data)
*
*
*
* @param[in] pSciMapTbl - Table data pointer
* @param[in] FchResetDataBlock
*
*/
VOID
ProgramFchSciMapTbl (
IN SCI_MAP_CONTROL *pSciMapTbl,
IN FCH_RESET_DATA_BLOCK *FchResetDataBlock
)
{
AMD_CONFIG_PARAMS *StdHeader;
UINT32 ddtempVar;
StdHeader = FchResetDataBlock->StdHeader;
if (pSciMapTbl != NULL) {
while (pSciMapTbl->InputPin != 0xFF) {
if ((pSciMapTbl->InputPin >= 0x40) && (pSciMapTbl->InputPin < 0x80) && (pSciMapTbl->GpeMap < 0x20)) {
ddtempVar = ACPI_MMIO_BASE | SMI_BASE | pSciMapTbl->InputPin;
if (((pSciMapTbl->InputPin == FCH_SMI_xHC0Pme) && (FchResetDataBlock->FchReset.Xhci0Enable == 0)) || \
((pSciMapTbl->InputPin == FCH_SMI_xHC1Pme) && (FchResetDataBlock->FchReset.Xhci1Enable == 0))) {
} else {
LibAmdMemWrite (AccessWidth8, (UINT64) ddtempVar, &pSciMapTbl->GpeMap, StdHeader);
}
} else {
//Assert Warning "SCI map is invalid"
}
pSciMapTbl++;
}
}
}
/*----------------------------------------------------------------------------------------*/
/**
* ProgramFchGpioTbl - Program FCH Gpio table (8 bits data)
*
*
*
* @param[in] pGpioTbl - Table data pointer
*
*/
VOID
ProgramFchGpioTbl (
IN GPIO_CONTROL *pGpioTbl
)
{
if (pGpioTbl != NULL) {
while (pGpioTbl->GpioPin != 0xFF) {
ACPIMMIO8 (ACPI_MMIO_BASE + IOMUX_BASE + pGpioTbl->GpioPin) = (UINT8) (pGpioTbl->PinFunction);
ACPIMMIO8 (ACPI_MMIO_BASE + GPIO_BANK0_BASE + (pGpioTbl->GpioPin << 2) + 2) = (UINT8) (pGpioTbl->CfgByte);
pGpioTbl++;
}
}
}
/*----------------------------------------------------------------------------------------*/
/**
* ProgramSataPhyTbl - Program FCH Sata Phy table (8 bits data)
*
*
*
* @param[in] pSataPhyTbl - Table data pointer
* @param[in] FchResetDataBlock
*
*/
VOID
ProgramFchSataPhyTbl (
IN SATA_PHY_CONTROL *pSataPhyTbl,
IN FCH_RESET_DATA_BLOCK *FchResetDataBlock
)
{
if (pSataPhyTbl != NULL) {
while (pSataPhyTbl->PhyData != 0xFFFFFFFF) {
//to be implemented
pSataPhyTbl++;
}
}
}
#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) */
/**
* GetChipSysMode - Get Chip status
*
@ -180,299 +93,3 @@ IsImcEnabled (
}
}
#if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT)
/*----------------------------------------------------------------------------------------*/
/**
* SbSleepTrapControl - SB Sleep Trap Control
*
*
*
* @param[in] SleepTrap - Whether sleep trap is enabled
*
*/
VOID
SbSleepTrapControl (
IN BOOLEAN SleepTrap
)
{
if (SleepTrap) {
ACPIMMIO32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0) &= ~(BIT2 + BIT3);
ACPIMMIO32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0) |= BIT2;
ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGBE) &= ~ (BIT5);
ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xB) &= ~ (BIT0 + BIT1);
ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xB) |= BIT1;
} else {
ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGBE) |= BIT5;
ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xB) &= ~ (BIT0 + BIT1);
ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xB) |= BIT0;
ACPIMMIO32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0) &= ~(BIT2 + BIT3);
}
}
/**
* FchUsb3D3ColdCallback - Fch Usb3 D3Cold Callback
*
*
* @param[in] FchDataPtr
*
*/
VOID
FchUsb3D3ColdCallback (
IN VOID *FchDataPtr
)
{
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
UINT8 Value8;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//FCH_DEADLOOP ();
ACPIMMIO32 (FCH_AOACxA0_PwrGood_Control) |= FCH_AOACxA0_PwrGood_Control_SwUsb3SlpShutdown;
do {
} while ((ACPIMMIO32 (FCH_AOACxA0_PwrGood_Control) & FCH_AOACxA0_PwrGood_Control_SwUsb3SlpShutdown) == 0);
ACPIMMIO32 (FCH_XHC_PMx00_Configure0) |= FCH_XHC_PMx00_Configure0_U3P_D3Cold_PWRDN;
ACPIMMIO8 (FCH_AOACx6E_USB3_D3_CONTROL) &= ~ (AOAC_PWR_ON_DEV);
do {
} while ((ACPIMMIO8 (FCH_AOACx6F_USB3_D3_STATE) & 0x07) != 0);
ACPIMMIO8 (FCH_AOACx6E_USB3_D3_CONTROL) |= 3;
ACPIMMIO32 (FCH_MISCx28_ClkDrvStr2) |= FCH_MISCx28_ClkDrvStr2_USB3_RefClk_Pwdn;
if ((ACPIMMIO8 (FCH_AOACx64_EHCI_D3_CONTROL) & 0x03) == 3) {
ACPIMMIO32 (FCH_AOACxA0_PwrGood_Control) &= ~ (FCH_AOACxA0_PwrGood_Control_SwUsb2S5RstB + FCH_AOACxA0_PwrGood_Control_SwUsb3SlpShutdown);
ACPIMMIO32 (FCH_MISCx28_ClkDrvStr2) |= FCH_MISCx28_ClkDrvStr2_USB2_RefClk_Pwdn;
}
ACPIMMIO32 (FCH_AOACxA0_PwrGood_Control) &= ~ (FCH_AOACxA0_PwrGood_Control_XhcPwrGood + FCH_AOACxA0_PwrGood_Control_SwUsb3SlpShutdown);
Value8 = ACPIMMIO8 (0xFED803EE);
Value8 &= 0xFC;
Value8 |= 0x01;
ACPIMMIO8 (0xFED803EE) = Value8;
}
/**
* FchUsb3D0Callback - Fch Usb3 D0 Callback
*
*
* @param[in] FchDataPtr
*
*/
VOID
FchUsb3D0Callback (
IN VOID *FchDataPtr
)
{
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
UINT32 Dword32;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
ACPIMMIO8 (0xFED803EE) &= 0xFC;
ACPIMMIO8 (FCH_AOACxA0_PwrGood_Control) |= (FCH_AOACxA0_PwrGood_Control_XhcPwrGood);
ACPIMMIO32 (FCH_MISCx28_ClkDrvStr2) &= ~ (FCH_MISCx28_ClkDrvStr2_USB2_RefClk_Pwdn);
ACPIMMIO32 (FCH_MISCx28_ClkDrvStr2) &= ~ (FCH_MISCx28_ClkDrvStr2_USB3_RefClk_Pwdn);
Dword32 = ACPIMMIO32 (FCH_AOACxA0_PwrGood_Control);
Dword32 &= ~(FCH_AOACxA0_PwrGood_Control_SwUsb3SlpShutdown);
ACPIMMIO32 (FCH_AOACxA0_PwrGood_Control) = ((FCH_AOACxA0_PwrGood_Control_SwUsb2S5RstB | Dword32) & (~ BIT29));
ACPIMMIO8 (FCH_AOACx6E_USB3_D3_CONTROL) &= 0xFC;
ACPIMMIO8 (FCH_AOACx6E_USB3_D3_CONTROL) |= (AOAC_PWR_ON_DEV);
do {
} while ((ACPIMMIO8 (FCH_AOACx6F_USB3_D3_STATE) & 0x07) != 7);
do {
} while ((ACPIMMIO32 (FCH_XHC_PMx00_Configure0) & BIT7) != BIT7);
ACPIMMIO32 (FCH_XHC_PMx00_Configure0) &= ~ (BIT16);
}
/* -----------------------------------------------------------------------------*/
/**
*
*
* This function Checks Bristol or Stoney
*
* NOTE:
*
* @param[in] StdHeader
*
*/
BOOLEAN
FchCheckBR_ST (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
CPU_LOGICAL_ID LogicalId;
// Only initialize on CZ processors, otherwise exit.
GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
if ((LogicalId.Revision & AMD_F15_BR_ALL) != 0) {
return TRUE;
}
if ((LogicalId.Revision & AMD_F15_ST_ALL) != 0) {
return TRUE;
}
return FALSE;
}
/* -----------------------------------------------------------------------------*/
/**
*
*
* This function Checks Bristol
*
* NOTE:
*
* @param[in] StdHeader
*
*/
BOOLEAN
FchCheckBR (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
CPU_LOGICAL_ID LogicalId;
// Only initialize on CZ processors, otherwise exit.
GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
if ((LogicalId.Revision & AMD_F15_BR_ALL) != 0) {
return TRUE;
}
return FALSE;
}
/* -----------------------------------------------------------------------------*/
/**
*
*
* This function Checks Stoney
*
* NOTE:
*
* @param[in] StdHeader
*
*/
BOOLEAN
FchCheckST (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
CPU_LOGICAL_ID LogicalId;
// Only initialize on CZ processors, otherwise exit.
GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
if ((LogicalId.Revision & AMD_F15_ST_ALL) != 0) {
return TRUE;
}
return FALSE;
}
/* -----------------------------------------------------------------------------*/
/**
*
*
* This function Checks Carrizo
*
* NOTE:
*
* @param[in] StdHeader
*
*/
BOOLEAN
FchCheckCZ (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
CPU_LOGICAL_ID LogicalId;
// Only initialize on CZ processors, otherwise exit.
GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
if ((LogicalId.Revision & AMD_F15_CZ_ALL) != 0) {
return TRUE;
}
return FALSE;
}
/* -----------------------------------------------------------------------------*/
/**
*
*
* This function Checks Package AM4
*
* NOTE:
*
* @param[in] StdHeader
*
*/
BOOLEAN
FchCheckPackageAM4 (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
CPUID_DATA CpuId;
UINT8 RegValue;
LibAmdCpuidRead (AMD_CPUID_FMF, &CpuId, StdHeader);
RegValue = (UINT8) (CpuId.EBX_Reg >> 28) & 0xF; // bit 31:28
///@todo - update the PkgType once it is reflected in BKDG
if (RegValue == 2) {
return TRUE;
} else {
return FALSE;
}
}
/* -----------------------------------------------------------------------------*/
/**
*
*
* This function Get Scratch Fuse
*
* NOTE:
*
* @param[in] StdHeader
*
*/
UINT64
FchGetScratchFuse (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
PCI_ADDR D0F0xB8_SMU_Index_Address;
PCI_ADDR D0F0xBC_SMU_Index_Data;
UINT64 TempData64;
UINT32 TempData32;
D0F0xB8_SMU_Index_Address.AddressValue = (MAKE_SBDFO (0, 0, 0, 0, 0xB8));
D0F0xBC_SMU_Index_Data.AddressValue = (MAKE_SBDFO (0, 0, 0, 0, 0xBC));
TempData64 = 0;
TempData32 = 0xC0016028;
LibAmdPciWrite (AccessWidth32, D0F0xB8_SMU_Index_Address, &TempData32, StdHeader);
LibAmdPciRead (AccessWidth32, D0F0xBC_SMU_Index_Data, &TempData32, StdHeader);
TempData64 |= (((UINT64) TempData32) & 0xFFFFFFFF) >> 9;
TempData32 = 0xC001602C;
LibAmdPciWrite (AccessWidth32, D0F0xB8_SMU_Index_Address, &TempData32, StdHeader);
LibAmdPciRead (AccessWidth32, D0F0xBC_SMU_Index_Data, &TempData32, StdHeader);
TempData64 |= (((UINT64) TempData32) & 0xFFFFFFFF) << (32 - 9);
TempData32 = 0xC0016030;
LibAmdPciWrite (AccessWidth32, D0F0xB8_SMU_Index_Address, &TempData32, StdHeader);
LibAmdPciRead (AccessWidth32, D0F0xBC_SMU_Index_Data, &TempData32, StdHeader);
TempData64 |= (((UINT64) TempData32) & 0xFFFFFFFF) << (64 - 9);
return TempData64;
}
#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) */