soc/apollolake: Add helper functions to access Power Management Registers
Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
This commit is contained in:
Hannah Williams
Martin Roth
parent
9c6c791351
commit
01bc897dfa
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@ -26,8 +26,10 @@ romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
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romstage-y += memmap.c
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romstage-y += mmap_boot.c
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romstage-y += tsc_freq.c
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romstage-y += pmutil.c
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smm-y += placeholders.c
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smm-y += pmutil.c
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ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
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ramstage-y += cpu.c
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@ -42,6 +44,7 @@ ramstage-y += uart.c
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ramstage-y += northbridge.c
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ramstage-y += spi.c
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ramstage-y += tsc_freq.c
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ramstage-y += pmutil.c
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postcar-y += exit_car.S
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postcar-y += memmap.c
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corp.
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* Copyright (C) 2015-2016 Intel Corp.
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* (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
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*
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* This program is free software; you can redistribute it and/or modify
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@ -18,19 +18,130 @@
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#ifndef _SOC_APOLLOLAKE_PM_H_
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#define _SOC_APOLLOLAKE_PM_H_
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/* ACPI_BASE_ADDRESS / PMBASE */
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#include <stdint.h>
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/* ACPI_BASE_ADDRESS */
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#define PM1_STS 0x00
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#define WAK_STS (1 << 15)
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#define PWRBTN_STS (1 << 8)
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#define PM1_EN 0x02
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#define PCIEXPWAK_DIS (1 << 14)
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#define USB_WAKE_EN (1 << 13)
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#define RTC_EN (1 << 10)
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#define PWRBTN_EN (1 << 8)
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#define GBL_EN (1 << 5)
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#define TMROF_EN (1 << 0)
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#define PM1_CNT 0x04
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#define SLP_EN (1 << 13)
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#define SLP_TYP_SHIFT 10
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#define SLP_TYP (7 << SLP_TYP_SHIFT)
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#define SLP_TYP_S0 0
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#define SLP_TYP_S3 5
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#define SLP_TYP_S4 6
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#define SLP_TYP_S5 7
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#define SCI_EN (1 << 0)
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#define PM1_TMR 0x08
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#define SMI_EN 0x40
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#define SMI_OCP_CSE 27
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#define SMI_SPI 26
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#define SMI_SPI_SSMI 25
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#define SMI_SCC2 21
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#define SMI_PCIE 20
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#define SMI_SCS 19
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#define SMI_HOST_SMBUS 18
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#define SMI_XHCI 17
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#define SMI_SMBUS 16
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#define SMI_SERIRQ 15
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#define SMI_PERIODIC 14
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#define SMI_TCO 13
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#define SMI_MCSMI 12
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#define SMI_GPIO_UNLOCK_SSMI 11
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#define SMI_GPIO 10
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#define SMI_BIOS_RLS 7
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#define SMI_SWSMI_TMR 6
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#define SMI_APMC 5
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#define SMI_SLP 4
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#define SMI_LEGACY_USB 3
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#define SMI_BIOS 2
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#define SMI_EOS 1
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#define SMI_GBL 0
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#define USB_EN (1 << SMI_XHCI) /* Legacy USB2 SMI logic */
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#define PERIODIC_EN (1 << SMI_PERIODIC) /* SMI on PERIODIC_STS in SMI_STS */
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#define TCO_EN (1 << SMI_TCO) /* Enable TCO Logic (BIOSWE et al) */
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#define BIOS_RLS (1 << SMI_BIOS_RLS) /* asserts SCI on bit set */
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#define SWSMI_TMR_EN (1 << SMI_SWSMI_TMR) /* start software smi timer on bit set */
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#define APMC_EN (1 << SMI_APMC) /* Writes to APM_CNT cause SMI# */
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#define SLP_SMI_EN (1 << SMI_SLP) /* Write to SLP_EN in PM1_CNT asserts SMI# */
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#define BIOS_EN (1 << SMI_BIOS) /* Assert SMI# on GBL_RLS bit */
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#define EOS (1 << SMI_EOS) /* End of SMI (deassert SMI#) */
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#define GBL_SMI_EN (1 << SMI_GBL) /* Global SMI Enable */
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#define SMI_STS 0x44
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#define GPE_CNTL 0x50
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#define DEVACT_STS 0x4c
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#define TCO_STS 0x64
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#define TCO_TIMEOUT (1 << 3)
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#define TCO1_CNT 0x68
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#define GPE0_REG_MAX 4
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#define GPE0_REG_SIZE 32
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#define GPE0_STS(x) (0x20 + (x * 4))
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#define GPE0_EN(x) (0x30 + (x * 4))
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#define PME_B0_EN (1 << 13)
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#endif /* _SOC_APOLLOLAKE_PM_H_ */
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/* Memory mapped IO registers behind PMC_BASE_ADDRESS */
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#define PRSTS 0x1000
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#define GEN_PMCON1 0x1020
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# define PWR_FLR (1 << 16)
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# define SUS_PWR_FLR (1 << 14)
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#define GEN_PMCON2 0x1024
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# define RPS (1 << 2)
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#define GEN_PMCON3 0x1028
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/* Generic sleep state types */
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#define SLEEP_STATE_S0 0
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#define SLEEP_STATE_S3 3
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#define SLEEP_STATE_S5 5
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/* Track power state from reset to log events. */
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struct chipset_power_state {
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uint16_t pm1_sts;
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uint16_t pm1_en;
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uint32_t pm1_cnt;
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uint32_t gpe0_sts[GPE0_REG_MAX];
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uint32_t gpe0_en[GPE0_REG_MAX];
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uint32_t tco_sts;
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uint32_t prsts;
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uint32_t gen_pmcon1;
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uint32_t gen_pmcon2;
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uint32_t gen_pmcon3;
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uint32_t prev_sleep_state;
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} __attribute__((packed));
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int fill_power_state(struct chipset_power_state *ps);
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int chipset_prev_sleep_state(struct chipset_power_state *ps);
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/* Power Management Utility Functions. */
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uint32_t clear_smi_status(void);
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uint16_t clear_pm1_status(void);
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uint32_t clear_tco_status(void);
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uint32_t clear_gpe_status(void);
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void clear_pmc_status(void);
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uint32_t get_smi_en(void);
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void enable_smi(uint32_t mask);
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void disable_smi(uint32_t mask);
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void enable_pm1(uint16_t events);
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void enable_pm1_control(uint32_t mask);
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void disable_pm1_control(uint32_t mask);
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void enable_gpe(uint32_t mask);
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void disable_gpe(uint32_t mask);
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void disable_all_gpe(void);
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#endif
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@ -0,0 +1,327 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2015-2016 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <rules.h>
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#include <device/pci_def.h>
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#include <soc/iomap.h>
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#include <soc/pm.h>
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#include <device/device.h>
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#include <device/pci.h>
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static void print_num_status_bits(int num_bits, uint32_t status,
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const char * const bit_names[])
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{
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int i;
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if (!status)
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return;
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for (i = num_bits - 1; i >= 0; i--) {
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if (status & (1 << i)) {
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if (bit_names[i])
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printk(BIOS_DEBUG, "%s ", bit_names[i]);
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else
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printk(BIOS_DEBUG, "BIT%d ", i);
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}
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}
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}
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static uint32_t print_smi_status(uint32_t smi_sts)
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{
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static const char * const smi_sts_bits[] = {
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[2] = "BIOS",
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[3] = "LEGACY USB",
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[4] = "SLP_SMI",
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[5] = "APM",
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[6] = "SWSMI_TMR",
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[10]= "GPIO_SMI",
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[11]= "GPIO_UNLOCK_SSMI",
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[12] = "MCSMI",
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[13] = "TCO",
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[14] = "PERIODIC",
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[15] = "SERIRQ",
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[16] = "SMBUS_SMI",
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[17] = "XHCI",
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[18] = "HOST_SMBUS",
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[19] = "SCS",
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[20] = "PCI_EXP_SMI",
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[21] = "SCC2",
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[25] = "SPI_SSMI",
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[26] = "SPI",
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[27] = "OCP_CSE",
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};
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if (!smi_sts)
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return 0;
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printk(BIOS_DEBUG, "SMI_STS: ");
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print_num_status_bits(ARRAY_SIZE(smi_sts_bits), smi_sts, smi_sts_bits);
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printk(BIOS_DEBUG, "\n");
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return smi_sts;
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}
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static uint32_t reset_smi_status(void)
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{
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uint32_t smi_sts = inl(ACPI_PMIO_BASE + SMI_STS);
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outl(smi_sts, ACPI_PMIO_BASE + SMI_STS);
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return smi_sts;
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}
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uint32_t clear_smi_status(void)
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{
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return print_smi_status(reset_smi_status());
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}
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uint32_t get_smi_en(void)
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{
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return inl(ACPI_PMIO_BASE + SMI_EN);
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}
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void enable_smi(uint32_t mask)
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{
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uint32_t smi_en = inl(ACPI_PMIO_BASE + SMI_EN);
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smi_en |= mask;
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outl(smi_en, ACPI_PMIO_BASE + SMI_EN);
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}
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void disable_smi(uint32_t mask)
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{
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uint32_t smi_en = inl(ACPI_PMIO_BASE + SMI_EN);
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smi_en &= ~mask;
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outl(smi_en, ACPI_PMIO_BASE + SMI_EN);
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}
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void enable_pm1_control(uint32_t mask)
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{
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uint32_t pm1_cnt = inl(ACPI_PMIO_BASE + PM1_CNT);
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pm1_cnt |= mask;
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outl(pm1_cnt, ACPI_PMIO_BASE + PM1_CNT);
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}
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void disable_pm1_control(uint32_t mask)
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{
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uint32_t pm1_cnt = inl(ACPI_PMIO_BASE + PM1_CNT);
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pm1_cnt &= ~mask;
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outl(pm1_cnt, ACPI_PMIO_BASE + PM1_CNT);
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}
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static uint16_t reset_pm1_status(void)
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{
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uint16_t pm1_sts = inw(ACPI_PMIO_BASE + PM1_STS);
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outw(pm1_sts, ACPI_PMIO_BASE + PM1_STS);
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return pm1_sts;
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}
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static uint16_t print_pm1_status(uint16_t pm1_sts)
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{
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static const char * const pm1_sts_bits[] = {
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[0] = "TMROF",
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[5] = "GBL",
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[8] = "PWRBTN",
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[10] = "RTC",
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[11] = "PRBTNOR",
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[13] = "USB",
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[14] = "PCIEXPWAK",
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[15] = "WAK",
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};
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if (!pm1_sts)
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return 0;
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printk(BIOS_SPEW, "PM1_STS: ");
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print_num_status_bits(ARRAY_SIZE(pm1_sts_bits), pm1_sts, pm1_sts_bits);
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printk(BIOS_SPEW, "\n");
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return pm1_sts;
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}
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uint16_t clear_pm1_status(void)
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{
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return print_pm1_status(reset_pm1_status());
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}
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void enable_pm1(uint16_t events)
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{
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outw(events, ACPI_PMIO_BASE + PM1_EN);
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}
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static uint32_t print_tco_status(uint32_t tco_sts)
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{
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static const char * const tco_sts_bits[] = {
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[3] = "TIMEOUT",
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[17] = "SECOND_TO",
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};
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if (!tco_sts)
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return 0;
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printk(BIOS_DEBUG, "TCO_STS: ");
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print_num_status_bits(ARRAY_SIZE(tco_sts_bits), tco_sts, tco_sts_bits);
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printk(BIOS_DEBUG, "\n");
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return tco_sts;
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}
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static uint32_t reset_tco_status(void)
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{
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uint32_t tco_sts = inl(ACPI_PMIO_BASE + TCO_STS);
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uint32_t tco_en = inl(ACPI_PMIO_BASE + TCO1_CNT);
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outl(tco_sts, ACPI_PMIO_BASE + TCO_STS);
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return tco_sts & tco_en;
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}
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uint32_t clear_tco_status(void)
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{
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return print_tco_status(reset_tco_status());
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}
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void enable_gpe(uint32_t mask)
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{
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uint32_t gpe0a_en = inl(ACPI_PMIO_BASE + GPE0_EN(0));
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gpe0a_en |= mask;
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outl(gpe0a_en, ACPI_PMIO_BASE + GPE0_EN(0));
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}
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void disable_gpe(uint32_t mask)
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{
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uint32_t gpe0a_en = inl(ACPI_PMIO_BASE + GPE0_EN(0));
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gpe0a_en &= ~mask;
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outl(gpe0a_en, ACPI_PMIO_BASE + GPE0_EN(0));
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}
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void disable_all_gpe(void)
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{
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disable_gpe(~0);
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}
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static uint32_t reset_gpe_status(void)
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{
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uint32_t gpe_sts = inl(ACPI_PMIO_BASE + GPE0_STS(0));
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outl(gpe_sts, ACPI_PMIO_BASE + GPE0_STS(0));
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return gpe_sts;
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}
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static uint32_t print_gpe_sts(uint32_t gpe_sts)
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{
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static const char * const gpe_sts_bits[] = {
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[0] = "PCIE_SCI",
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[2] = "SWGPE",
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[3] = "PCIE_WAKE0",
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[4] = "PUNIT",
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[6] = "PCIE_WAKE1",
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[7] = "PCIE_WAKE2",
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[8] = "PCIE_WAKE3",
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[9] = "PCI_EXP",
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[10] = "BATLOW",
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[11] = "CSE_PME",
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[12] = "XDCI_PME",
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[13] = "XHCI_PME",
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[14] = "AVS_PME",
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[15] = "GPIO_TIER1_SCI",
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[16] = "SMB_WAK",
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[17] = "SATA_PME",
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};
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if (!gpe_sts)
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return gpe_sts;
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printk(BIOS_DEBUG, "GPE0a_STS: ");
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print_num_status_bits(ARRAY_SIZE(gpe_sts_bits), gpe_sts, gpe_sts_bits);
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printk(BIOS_DEBUG, "\n");
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return gpe_sts;
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}
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uint32_t clear_gpe_status(void)
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{
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return print_gpe_sts(reset_gpe_status());
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}
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void clear_pmc_status(void)
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{
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uint32_t prsts;
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uint32_t gen_pmcon1;
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prsts = read32((void *)(PMC_BAR0 + PRSTS));
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gen_pmcon1 = read32((void *)(PMC_BAR0 + GEN_PMCON1));
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/* Clear the status bits. The RPS field is cleared on a 0 write. */
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write32((void *)(PMC_BAR0 + GEN_PMCON1), gen_pmcon1 & ~RPS);
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write32((void *)(PMC_BAR0 + PRSTS), prsts);
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}
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/* Return 0, 3, or 5 to indicate the previous sleep state. */
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int chipset_prev_sleep_state(struct chipset_power_state *ps)
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{
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/* Default to S0. */
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int prev_sleep_state = SLEEP_STATE_S0;
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if (ps->pm1_sts & WAK_STS) {
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switch ((ps->pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) {
|
||||
#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
|
||||
case SLP_TYP_S3:
|
||||
prev_sleep_state = SLEEP_STATE_S3;
|
||||
break;
|
||||
#endif
|
||||
case SLP_TYP_S5:
|
||||
prev_sleep_state = SLEEP_STATE_S5;
|
||||
break;
|
||||
}
|
||||
}
|
||||
return prev_sleep_state;
|
||||
}
|
||||
|
||||
/* returns prev_sleep_state */
|
||||
int fill_power_state(struct chipset_power_state *ps)
|
||||
{
|
||||
int i;
|
||||
ps->pm1_sts = inw(ACPI_PMIO_BASE + PM1_STS);
|
||||
ps->pm1_en = inw(ACPI_PMIO_BASE + PM1_EN);
|
||||
ps->pm1_cnt = inl(ACPI_PMIO_BASE + PM1_CNT);
|
||||
ps->tco_sts = inl(ACPI_PMIO_BASE + TCO_STS);
|
||||
ps->prsts = read32((void *)(PMC_BAR0 + PRSTS));
|
||||
ps->gen_pmcon1 =read32((void *)(PMC_BAR0 + GEN_PMCON1));
|
||||
ps->gen_pmcon2 = read32((void *)(PMC_BAR0 + GEN_PMCON2));
|
||||
ps->gen_pmcon3 = read32((void *)(PMC_BAR0 + GEN_PMCON3));
|
||||
|
||||
ps->prev_sleep_state = chipset_prev_sleep_state(ps);
|
||||
|
||||
printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n",
|
||||
ps->pm1_sts, ps->pm1_en, ps->pm1_cnt);
|
||||
printk(BIOS_DEBUG, "prsts: %08x tco_sts: %08x\n",
|
||||
ps->prsts, ps->tco_sts);
|
||||
printk(BIOS_DEBUG,
|
||||
"gen_pmcon1: %08x gen_pmcon2: %08x gen_pmcon3: %08x\n",
|
||||
ps->gen_pmcon1, ps->gen_pmcon2, ps->gen_pmcon3);
|
||||
printk(BIOS_DEBUG, "smi_en: %08x smi_sts: %08x\n",
|
||||
inl(ACPI_PMIO_BASE + SMI_EN), inl(ACPI_PMIO_BASE + SMI_STS));
|
||||
for (i=0; i < GPE0_REG_MAX; i++) {
|
||||
ps->gpe0_sts[i] = inl(ACPI_PMIO_BASE + GPE0_STS(i));
|
||||
ps->gpe0_en[i] = inl(ACPI_PMIO_BASE + GPE0_EN(i));
|
||||
printk(BIOS_DEBUG, "gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n",
|
||||
i, ps->gpe0_sts[i], i, ps->gpe0_en[i]);
|
||||
}
|
||||
printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state);
|
||||
return ps->prev_sleep_state;
|
||||
}
|
||||
Loading…
Reference in New Issue