Add sb800 spi support.
It is for S3, storing the recovring data in the nonvolatile storage, i.e., flash. Change-Id: Ie9e4f42a80c93d92d2e442f0e833ce06d88294f9 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/620 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
This commit is contained in:
zbao
Marc Jones
parent
971804ed68
commit
01bd79ff69
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@ -27,6 +27,8 @@ romstage-y += smbus.c
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ramstage-y += cfg.c
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ramstage-y += cfg.c
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ramstage-y += late.c
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ramstage-y += late.c
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ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c
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driver-y += smbus.c
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driver-y += smbus.c
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driver-y += lpc.c
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driver-y += lpc.c
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@ -158,4 +158,8 @@ typedef union _PCI_ADDR {
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#include "vendorcode/amd/cimx/sb800/AMDSBLIB.h"
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#include "vendorcode/amd/cimx/sb800/AMDSBLIB.h"
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#if CONFIG_HAVE_ACPI_RESUME == 1
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#include "spi.h"
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#endif
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#endif // _AMD_SBPLATFORM_H_
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#endif // _AMD_SBPLATFORM_H_
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@ -0,0 +1,209 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <arch/io.h>
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#include <device/device.h>
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#include "SBPLATFORM.h"
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void execute_command(volatile u8 * spi_address)
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{
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*(spi_address + 2) |= 1;
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}
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void wait4command_complete(volatile u8 * spi_address)
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{
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while (*(spi_address + 2) & 1)
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printk(BIOS_DEBUG, "wait4CommandComplete\n");
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}
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void reset_internal_fifo_pointer(volatile u8 * spi_address)
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{
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u8 val;
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do {
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*(spi_address + 2) |= 0x10;
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val = *(spi_address + 0xd);
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} while (val & 0x7);
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}
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u8 read_spi_status(volatile u8 * spi_address)
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{
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u8 val;
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*spi_address = 0x05;
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*(spi_address + 1) = 0x11;
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reset_internal_fifo_pointer(spi_address);
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*(spi_address + 0xC) = 0x0; /* dummy */
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reset_internal_fifo_pointer(spi_address);
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execute_command(spi_address);
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wait4command_complete(spi_address);
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reset_internal_fifo_pointer(spi_address);
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val = *(spi_address + 0xC);
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val = *(spi_address + 0xC);
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return val;
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}
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void wait4flashpart_ready(volatile u8 * spi_address)
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{
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while (read_spi_status(spi_address) & 1) ;
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}
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void write_spi_status(volatile u8 * spi_address, u8 status)
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{
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*spi_address = 0x50; /* EWSR */
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*(spi_address + 1) = 0; /* RxByte=TxByte=0 */
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execute_command(spi_address);
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wait4command_complete(spi_address);
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*spi_address = 0x01; /* WRSR */
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*(spi_address + 1) = 0x01;
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reset_internal_fifo_pointer(spi_address);
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*(spi_address + 0xC) = status;
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reset_internal_fifo_pointer(spi_address);
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execute_command(spi_address);
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wait4command_complete(spi_address);
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wait4flashpart_ready(spi_address);
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read_spi_status(spi_address);
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}
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void read_spi_id(volatile u8 * spi_address)
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{
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u8 mid = 0, did = 0;
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*spi_address = 0x90;
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*(spi_address + 1) = 0x23; /* RxByte=2, TxByte=3 */
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reset_internal_fifo_pointer(spi_address);
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*(spi_address + 0xC) = 0;
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*(spi_address + 0xC) = 0;
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*(spi_address + 0xC) = 0;
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reset_internal_fifo_pointer(spi_address);
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execute_command(spi_address);
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wait4command_complete(spi_address);
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reset_internal_fifo_pointer(spi_address);
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mid = *(spi_address + 0xC);
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printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did);
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mid = *(spi_address + 0xC);
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printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did);
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mid = *(spi_address + 0xC);
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printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did);
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mid = *(spi_address + 0xC);
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did = *(spi_address + 0xC);
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printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did);
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}
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void spi_write_enable(volatile u8 * spi_address)
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{
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*spi_address = 0x06; /* Write Enable */
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*(spi_address + 1) = 0x0; /* RxByte=0, TxByte=0 */
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execute_command(spi_address);
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wait4command_complete(spi_address);
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}
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void sector_erase_spi(volatile u8 * spi_address, u32 address)
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{
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spi_write_enable(spi_address);
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*spi_address = 0x20;
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*(spi_address + 1) = 0x03; /* RxByte=0, TxByte=3 */
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reset_internal_fifo_pointer(spi_address);
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*(spi_address + 0xC) = (address >> 16) & 0xFF;
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*(spi_address + 0xC) = (address >> 8) & 0xFF;
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*(spi_address + 0xC) = (address >> 0) & 0xFF;
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reset_internal_fifo_pointer(spi_address);
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execute_command(spi_address);
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wait4command_complete(spi_address);
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wait4flashpart_ready(spi_address);
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}
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void chip_erase_spi(volatile u8 * spi_address)
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{
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spi_write_enable(spi_address);
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*spi_address = 0xC7;
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*(spi_address + 1) = 0x00;
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execute_command(spi_address);
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wait4command_complete(spi_address);
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wait4flashpart_ready(spi_address);
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}
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void byte_program(volatile u8 * spi_address, u32 address, u32 data)
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{
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spi_write_enable(spi_address);
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*spi_address = 0x02;
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*(spi_address + 1) = 0x0 << 4 | 4;
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reset_internal_fifo_pointer(spi_address);
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*(spi_address + 0xC) = (address >> 16) & 0xFF;
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*(spi_address + 0xC) = (address >> 8) & 0xFF;
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*(spi_address + 0xC) = (address >> 0) & 0xFF;
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*(spi_address + 0xC) = data & 0xFF;
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reset_internal_fifo_pointer(spi_address);
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execute_command(spi_address);
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wait4command_complete(spi_address);
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wait4flashpart_ready(spi_address);
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}
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void dword_noneAAI_program(volatile u8 * spi_address, u32 address, u32 data)
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{
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u8 i;
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/*
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* printk(BIOS_SPEW, "%s: addr=%x, data=%x\n", __func__, address, data);
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*/
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for (i = 0; i < 4; i++) {
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spi_write_enable(spi_address);
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*spi_address = 0x02;
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*(spi_address + 1) = 0x0 << 4 | 4;
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reset_internal_fifo_pointer(spi_address);
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*(spi_address + 0xC) = (address >> 16) & 0xFF;
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*(spi_address + 0xC) = (address >> 8) & 0xFF;
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*(spi_address + 0xC) = (address >> 0) & 0xFF;
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*(spi_address + 0xC) = data & 0xFF;
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data >>= 8;
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address++;
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reset_internal_fifo_pointer(spi_address);
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execute_command(spi_address);
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wait4command_complete(spi_address);
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wait4flashpart_ready(spi_address);
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}
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}
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void dword_program(volatile u8 * spi_address, u32 address, u32 data)
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{
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spi_write_enable(spi_address);
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*spi_address = 0x02;
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*(spi_address + 1) = 0x0 << 4 | 7;
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reset_internal_fifo_pointer(spi_address);
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*(spi_address + 0xC) = (address >> 16) & 0xFF;
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*(spi_address + 0xC) = (address >> 8) & 0xFF;
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*(spi_address + 0xC) = (address >> 0) & 0xFF;
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*(spi_address + 0xC) = data & 0xFF;
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*(spi_address + 0xC) = (data >> 8) & 0xFF;
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*(spi_address + 0xC) = (data >> 16) & 0xFF;
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*(spi_address + 0xC) = (data >> 24) & 0xFF;
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reset_internal_fifo_pointer(spi_address);
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execute_command(spi_address);
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wait4command_complete(spi_address);
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wait4flashpart_ready(spi_address);
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}
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void direct_byte_program(volatile u8 * spi_address, volatile u32 * address, u32 data)
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{
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spi_write_enable(spi_address);
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*address = data;
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wait4flashpart_ready(spi_address);
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}
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@ -0,0 +1,42 @@
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/*
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*****************************************************************************
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*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* ***************************************************************************
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*
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*/
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#ifndef _SB800_CIMX_SPI_H_
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#define _SB800_CIMX_SPI_H_
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void execute_command(volatile u8 * spi_address);
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void wait4command_complete(volatile u8 * spi_address);
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void reset_internal_fifo_pointer(volatile u8 * spi_address);
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u8 read_spi_status(volatile u8 * spi_address);
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void wait4flashpart_ready(volatile u8 * spi_address);
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void write_spi_status(volatile u8 * spi_address, u8 status);
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void read_spi_id(volatile u8 * spi_address);
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void spi_write_enable(volatile u8 * spi_address);
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void sector_erase_spi(volatile u8 * spi_address, u32 address);
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void chip_erase_spi(volatile u8 * spi_address);
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void byte_program(volatile u8 * spi_address, u32 address, u32 data);
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void dword_noneAAI_program(volatile u8 * spi_address, u32 address, u32 data);
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void dword_program(volatile u8 * spi_address, u32 address, u32 data);
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void direct_byte_program(volatile u8 * spi_address, volatile u32 * address, u32 data);
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#endif
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