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mb/google/rex: Update USB2-C1 mapping 

This patch updates the USB2-C1 mapping from USB2 Port 4 to USB2 Port 1
as per latest Rex schematics dated 12/06/2022.

TEST=Hardward awaited.

Change-Id: Ifc82200e6eafcea7e820a96df81325f3c8849fd1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70426
Reviewed-by: Eran Mitrani <mitrani@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2022-12-06 20:44:25 +05:30
parent 2bc46c9601
commit 01c190e382
1 changed files with 9 additions and 9 deletions
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18
src/mainboard/google/rex/variants/rex0/overridetree.cb
View File

@ -31,8 +31,8 @@ end
chip soc/intel/meteorlake
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0
register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera
register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # Type-A Port A0
@ -171,6 +171,13 @@ chip soc/intel/meteorlake
device ref xhci on
chip drivers/usb/acpi
device ref xhci_root_hub on
chip drivers/usb/acpi
register "desc" = ""USB2 Type-C Port C1 (DB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
device ref usb2_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-C Port C0 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
@ -178,13 +185,6 @@ chip soc/intel/meteorlake
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))"
device ref usb2_port2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-C Port C1 (DB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
device ref usb2_port4 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 WWAN""
register "type" = "UPC_TYPE_INTERNAL"
@ -536,7 +536,7 @@ chip soc/intel/meteorlake
device generic 0 alias conn0 on end
end
chip drivers/intel/pmc_mux/conn
use usb2_port4 as usb2_port
use usb2_port1 as usb2_port
use tcss_usb3_port3 as usb3_port
device generic 1 alias conn1 on end
end