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cubieboard: Enable the SD controller and mux SD pins 

This step needs to be done before calling any MMC functionality.

Change-Id: I88763072c8a541ddba794e79fb55e82eb2f187a9
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4745
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
This commit is contained in:
Alexandru Gagniuc 2013-12-28 15:10:28 -05:00
parent fccfee3bce
commit 01c44000be
2 changed files with 25 additions and 0 deletions
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10
src/cpu/allwinner/a10/clock.h
View File

@ -66,6 +66,16 @@
/* DRAM_CLK values*/
#define DRAM_CTRL_DCLK_OUT (1 << 15)
/* SDx_CLK values */
#define SDx_CLK_GATE (1 << 31)
#define SDx_CLK_SRC_MASK (3 << 24)
#define SDx_CLK_SRC_OSC24M (0 << 24)
#define SDx_CLK_SRC_PLL6 (1 << 24)
#define SDx_CLK_SRC_PLL5 (2 << 24)
#define SDx_RAT_EXP_N_MASK (3 << 16)
#define SDx_RAT_EXP_N(n) (((n) << 16) & SDx_RAT_EXP_N_MASK)
#define SDx_RAT_M_MASK (0xf << 0)
#define SDx_RAT_M(m) ((((m) - 1) << 0) & SDx_RAT_M_MASK)
/**
* \brief Clock gating definitions
*

15
src/mainboard/cubietech/cubieboard/bootblock.c
View File

@ -27,6 +27,10 @@
#define GPB_UART0_FUNC 2
#define GPB_UART0_PINS ((1 << 22) | (1 << 23))
#define GPF_SD0_FUNC 2
#define GPF_SD0_PINS 0x3f /* PF0 thru PF5 */
#define GPH1_SD0_DET_FUNC 5
static void cubieboard_set_sys_clock(void)
{
u32 reg32;
@ -60,6 +64,13 @@ static void cubieboard_setup_clocks(void)
write32(APB1_CLK_SRC_OSC24M | APB1_RAT_N(0) | APB1_RAT_M(0),
&ccm->apb1_clk_div_cfg);
/* Configure the clock for SD0 */
write32(SDx_CLK_GATE | SDx_CLK_SRC_OSC24M | SDx_RAT_EXP_N(0)
| SDx_RAT_M(1), &ccm->sd0_clk_cfg);
/* Enable clock to SD0 */
a1x_periph_clock_enable(A1X_CLKEN_MMC0);
}
static void cubieboard_setup_gpios(void)
@ -71,6 +82,10 @@ static void cubieboard_setup_gpios(void)
/* Mux UART pins */
gpio_set_multipin_func(GPB, GPB_UART0_PINS, GPB_UART0_FUNC);
/* Mux SD pins */
gpio_set_multipin_func(GPF, GPF_SD0_PINS, GPF_SD0_FUNC);
gpio_set_pin_func(GPH, 1, GPH1_SD0_DET_FUNC);
}
static void cubieboard_enable_uart(void)