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3rdparty/blobs: Update submodule, SNB improvements 

The sandybridge systemagent-r6 blob is modified:
- To be more flexible about the location of the stack w.r.t. the heap
- Place the MRC pool right below the MRC_VAR region
- to work with the same DCACHE_RAM_BASE from the native raminit (could
  make the CAR linker symbols easily compatible if desired)

This allows CAR setup compatibility between mrc.bin and native
bootpath and also allows for BIOS/memory mappeds region larger than
8MB.

This changes the semantics of CONFIG_DACHE_RAM_MRC_VAR_SIZE to also
include the pool on top of MRC_VAR region.

TESTED on T520 (boots and resumes from S3 with mrc.bin).

Change-Id: I17d240656575b69a24718d90e4f2d2b7339d05a7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33228
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2019-06-05 13:36:55 +02:00 committed by Nico Huber
parent 14774769da
commit 01c83a2e99
4 changed files with 30 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
3rdparty/blobs vendored

@ -1 +1 @@
Subproject commit ca6cfcdbe1cdeb38c2622ee2e5236cc4657e3377 Subproject commit d7600dd8718a076f0f9a89e53968b484254624dc

7
src/arch/x86/car.ld
View File

@ -91,13 +91,6 @@
_car_global_end = .; _car_global_end = .;
_car_relocatable_data_end = .; _car_relocatable_data_end = .;
#if CONFIG(NORTHBRIDGE_INTEL_SANDYBRIDGE) && !CONFIG(USE_NATIVE_RAMINIT)
. = ABSOLUTE(0xff7e1000);
_mrc_pool = .;
. += 0x5000;
_emrc_pool = .;
#endif
#if !CONFIG(C_ENVIRONMENT_BOOTBLOCK) #if !CONFIG(C_ENVIRONMENT_BOOTBLOCK)
_car_stack_start = .; _car_stack_start = .;
_car_stack_end = _car_region_end; _car_stack_end = _car_region_end;

13
src/northbridge/intel/sandybridge/Kconfig
View File

@ -78,12 +78,13 @@ config MMCONF_BASE_ADDRESS
help help
The MRC blob requires it to be at 0xf0000000. The MRC blob requires it to be at 0xf0000000.
if USE_NATIVE_RAMINIT
config DCACHE_RAM_BASE config DCACHE_RAM_BASE
hex hex
default 0xfefe0000 default 0xfefe0000
if USE_NATIVE_RAMINIT
config DCACHE_RAM_SIZE config DCACHE_RAM_SIZE
hex hex
default 0x20000 default 0x20000
@ -96,17 +97,13 @@ endif # USE_NATIVE_RAMINIT
if !USE_NATIVE_RAMINIT if !USE_NATIVE_RAMINIT
config DCACHE_RAM_BASE
hex
default 0xff7e0000
config DCACHE_RAM_SIZE config DCACHE_RAM_SIZE
hex hex
default 0x1c000 default 0x17000
config DCACHE_RAM_MRC_VAR_SIZE config DCACHE_RAM_MRC_VAR_SIZE
hex hex
default 0x4000 default 0x9000
config MRC_FILE config MRC_FILE
string "Intel System Agent path and filename" string "Intel System Agent path and filename"

26
src/northbridge/intel/sandybridge/raminit_mrc.c
View File

@ -265,9 +265,31 @@ void sdram_initialize(struct pei_data *pei_data)
report_memory_config(); report_memory_config();
} }
/* These are the location and structure of MRC_VAR data in CAR. */ /* These are the location and structure of MRC_VAR data in CAR.
The CAR region looks like this:
+------------------+ -> DCACHE_RAM_BASE
| |
| |
| COREBOOT STACK |
| |
| |
+------------------+ -> DCACHE_RAM_BASE + DCACHE_RAM_SIZE
| |
| MRC HEAP |
| size = 0x5000 |
| |
+------------------+
| |
| MRC VAR |
| size = 0x4000 |
| |
+------------------+ -> DACHE_RAM_BASE + DACHE_RAM_SIZE
+ DCACHE_RAM_MRC_VAR_SIZE
*/
#define DCACHE_RAM_MRC_VAR_BASE \ #define DCACHE_RAM_MRC_VAR_BASE \
(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE + \
CONFIG_DCACHE_RAM_MRC_VAR_SIZE - 0x4000)
struct mrc_var_data { struct mrc_var_data {
u32 acpi_timer_flag; u32 acpi_timer_flag;