soc/intel/common/block: Add Intel common UART code
Create Intel Common UART driver code. This code does below UART configuration for bootblock phase. * Program BAR * Configure reset register * Configure clock register Change-Id: I3843fac88cfb7bbb405be50d69f555b274f0d72a Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/18952 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef SOC_INTEL_COMMON_BLOCK_UART_H
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#define SOC_INTEL_COMMON_BLOCK_UART_H
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#include <arch/io.h>
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void uart_common_init(device_t dev, uintptr_t baseaddr,
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uint32_t clk_m_val, uint32_t clk_n_val);
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#endif /* SOC_INTEL_COMMON_BLOCK_UART_H */
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config SOC_INTEL_COMMON_BLOCK_UART
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bool
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select SOC_INTEL_COMMON_BLOCK_LPSS
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help
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Intel Processor common UART support
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bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_UART) += uart.c
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/pci_def.h>
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#include <intelblocks/lpss.h>
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#include <intelblocks/uart.h>
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void uart_common_init(device_t dev, uintptr_t baseaddr, uint32_t clk_m_val,
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uint32_t clk_n_val)
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{
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/* Set UART base address */
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pci_write_config32(dev, PCI_BASE_ADDRESS_0, baseaddr);
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/* Enable memory access and bus master */
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pci_write_config32(dev, PCI_COMMAND,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
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/* Take UART out of reset */
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lpss_reset_release(baseaddr);
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/* Set M and N divisor inputs and enable clock */
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lpss_clk_update(baseaddr, clk_m_val, clk_n_val);
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}
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