fixes for epia, attempts to fix arima
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1259 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
parent
8cb747942c
commit
01e375b401
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@ -219,7 +219,7 @@ static void main(void)
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memreset_setup();
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sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
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#if 0
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#if 1
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dump_pci_devices();
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#endif
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#if 0
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@ -131,7 +131,7 @@ end
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makerule ./failover.inc
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depends "./failover.E ./romcc"
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action "./romcc -O2 -mcpu=c3 -o failover.inc --label-prefix=failover ./failover.E"
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action "./romcc -O -mcpu=c3 -o failover.inc --label-prefix=failover ./failover.E"
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end
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makerule ./auto.E
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@ -140,7 +140,7 @@ makerule ./auto.E
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end
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makerule ./auto.inc
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depends "./auto.E ./romcc"
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action "./romcc -O2 -mcpu=c3 ./auto.E "
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action "./romcc -O -mcpu=c3 ./auto.E "
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end
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##
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@ -230,4 +230,3 @@ end
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##
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mainboardinit pc80/serial.inc
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mainboardinit arch/i386/lib/console.inc
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@ -1,7 +1,7 @@
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#define ASSEMBLY 1
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#define MAXIMUM_CONSOLE_LOGLEVEL 6
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#define DEFAULT_CONSOLE_LOGLEVEL 6
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//#define MAXIMUM_CONSOLE_LOGLEVEL 6
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//#define DEFAULT_CONSOLE_LOGLEVEL 6
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#include <stdint.h>
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#include <device/pci_def.h>
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@ -54,10 +54,6 @@ void dimms_read(unsigned long x)
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volatile unsigned long y;
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eax = x;
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for(c = 0; c < 6; c++) {
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print_debug("dimms_read: ");
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print_debug_hex32(eax);
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print_debug("\r\n");
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y = * (volatile unsigned long *) eax;
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eax += 0x10000000;
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}
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@ -68,9 +64,6 @@ void dimms_write(int x)
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uint8_t c;
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unsigned long eax = x;
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for(c = 0; c < 6; c++) {
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print_debug("dimms_write: ");
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print_debug_hex32(eax);
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print_debug("\r\n");
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*(volatile unsigned long *) eax = 0;
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eax += 0x10000000;
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}
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@ -109,14 +102,6 @@ dumpnorth(device_t north)
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static void sdram_set_registers(const struct mem_controller *ctrl)
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{
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static const uint16_t raminit_ma_reg_table[] = {
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/* Values for MA type register to try */
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0x0000, 0x8088, 0xe0ee,
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0xffff // end mark
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};
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static const unsigned char ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
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0x56, 0x57};
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device_t north = (device_t) 0;
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uint8_t c, r;
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@ -193,67 +178,64 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
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// high drive strength on MA[2: 13], we#, cas#, ras#
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// As per Cindy Lee, set to 0x37, not 0x57
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pci_write_config8(north,0x6D, 0x7f);
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/* Initialize all banks at once */
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}
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/* slot is the dram slot. Base is the *8M base. */
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static unsigned char
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do_module_size(unsigned char slot /*, unsigned char base) */)
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/* slot is the dram slot. Return size of side0 in lower 16-bit,
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* side1 in upper 16-bit, in units of 8MB */
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static unsigned long
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spd_module_size(unsigned char slot)
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{
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static const unsigned char log2[256] = {
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[1] = 0, [2] = 1, [4] = 2, [8] = 3,
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[16]=4, [32]=5, [64]=6,
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[128]=7
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};
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static const uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
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0x56, 0x57};
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device_t north = 0;
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/* for all the DRAMS, see if they are there and get the size of each
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* module. This is just a very early first cut at sizing.
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*/
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/* we may run out of registers ... */
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unsigned char width, banks, rows, cols, reg;
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unsigned char value = 0;
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unsigned char module = 0xa1 | (slot << 1);
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unsigned int banks, rows, cols, reg;
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unsigned int value = 0;
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unsigned int module = ((0x50 + slot) << 1) + 1;
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/* is the module there? if byte 2 is not 4, then we'll assume it
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* is useless.
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*/
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print_info("Slot ");
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print_info_hex8(slot);
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if (smbus_read_byte(module, 2) != 4) {
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print_err("Slot ");
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print_err_hex8(slot);
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print_err(" is empty\r\n");
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goto done;
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print_info(" is empty\r\n");
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return 0;
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}
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print_info(" is SDRAM ");
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//print_debug_hex8(slot);
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// print_debug(" is SDRAM\n");
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width = smbus_read_byte(module, 6) | (smbus_read_byte(module,7)<<0);
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banks = smbus_read_byte(module, 17);
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/* we're going to assume symmetric banks. Sorry. */
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cols = smbus_read_byte(module, 4) & 0xf;
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rows = smbus_read_byte(module, 3) & 0xf;
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/* grand total. You have rows+cols addressing, * times of banks, times
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* width of data in bytes */
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/* do this in terms of address bits. Then subtract 23 from it.
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* That might do it.
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*/
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value = cols + rows + log2[banks] + log2[width];
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value -= 23;
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/* now subtract 3 more bits as these are 8-bit bytes */
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value -= 3;
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// print_debug_hex8(value);
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// print_debug(" is the # bits for this bank\n");
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/* now put that size into the correct register */
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value = (1 << value);
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done:
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reg = ramregs[slot];
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/* Width is assumed to be 64 bits == 8 bytes */
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value = (1 << (cols + rows)) * banks * 8;
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print_info_hex32(value);
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print_info(" bytes ");
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/* Return in 8MB units */
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value >>= 23;
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// print_debug_hex8(value); print_debug(" would go into ");
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// print_debug_hex8(ramregs[reg]); print_debug("\n");
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// pci_write_config8(north, ramregs[reg], value);
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/* We should have single or double side */
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if (smbus_read_byte(module, 5) == 2) {
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print_info("x2");
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value = (value << 16) | value;
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}
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print_info("\r\n");
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return value;
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}
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static int
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spd_num_chips(unsigned char slot)
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{
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unsigned int module = ((0x50 + slot) << 1) + 1;
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unsigned int width;
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width = smbus_read_byte(module, 13);
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if (width == 0)
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width = 8;
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return 64 / width;
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}
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static void sdram_set_spd_registers(const struct mem_controller *ctrl)
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@ -283,20 +265,32 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
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*/
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}
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static void set_ma_mapping(device_t north, int slot, int type)
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{
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unsigned char reg, val;
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int shift;
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reg = 0x58 + slot/2;
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if (slot%2 >= 1)
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shift = 0;
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else
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shift = 4;
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val = pci_read_config8(north, reg);
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val &= ~(0xf << shift);
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val |= type << shift;
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pci_write_config8(north, reg, val);
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}
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static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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{
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unsigned char i;
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static const uint16_t raminit_ma_reg_table[] = {
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/* Values for MA type register to try */
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0x0000, 0x8088, 0xe0ee,
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0xffff // end mark
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};
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static const uint8_t ramregs[] = {
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0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57
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};
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device_t north = 0;
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uint8_t c, r, base;
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uint32_t size, base, slot, ma;
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/* begin to initialize*/
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// I forget why we need this, but we do
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dimms_write(0xa55a5aa5);
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@ -363,125 +357,38 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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// enable multi-page open
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pci_write_config8(north,0x6B, 0x0d);
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/* Begin auto-detection
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* Find the first bank with DIMM equipped. */
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/* Maximum possible memory in bank 0, none in other banks.
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* Starting from bank 0, we fill 0 in these registers
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* until memory is found. */
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pci_write_config8(north,0x5A, 0xff);
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pci_write_config8(north,0x5B, 0xff);
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pci_write_config8(north,0x5C, 0xff);
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pci_write_config8(north,0x5D, 0xff);
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pci_write_config8(north,0x5E, 0xff);
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pci_write_config8(north,0x5F, 0xff);
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pci_write_config8(north,0x56, 0xff);
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pci_write_config8(north,0x57, 0xff);
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dumpnorth(north);
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print_debug("MA\r\n");
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for(c = 0; c < 8; c++) {
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/* Write different values to 0 and 8, then read from 0.
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* If values of address 0 match, we have something there. */
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print_debug("write to 0\r\n");
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*(volatile unsigned long *) 0 = 0x12345678;
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/* LEAVE THIS HERE. IT IS ESSENTIAL. OTHERWISE BUFFERING
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* WILL FOOL YOU!
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*/
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print_debug("write to 8\r\n");
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*(volatile unsigned long *) 8 = 0x87654321;
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if (*(volatile unsigned long *) 0 != 0x12345678) {
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print_debug("no memory in this bank\r\n");
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/* No memory in this bank. Tell it to the bridge. */
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pci_write_config8(north,ramregs[c], 0);
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}
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/* found something */
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{
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uint8_t best = 0;
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/* Detect MA mapping type of the bank. */
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for(r = 0; r < 3; r++) {
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volatile unsigned long esi = 0;
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volatile unsigned long eax = 0;
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pci_write_config8(north,0x58, raminit_ma_reg_table[r]);
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* (volatile unsigned long *) eax = 0;
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print_debug(" done write to eax\r\n");
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// Write to addresses with only one address bit
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// on, from 0x80000000 to 0x00000008 (lower 3 bits
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// are ignored, assuming 64-bit bus). Then what
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// is read at address 0 is the value written to
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// the lowest address where it gets
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// wrap-around. That address is either the size of
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// the bank, or a missing bit due to incorrect MA
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// mapping.
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eax = 0x80000000;
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while (eax != 4) {
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* (volatile unsigned long *) eax = eax;
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//print_debug_hex32(eax);
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outb(eax&0xff, 0x80);
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eax >>= 1;
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}
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print_debug(" done read to eax\r\n");
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eax = * (unsigned long *)0;
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/* oh boy ... what is this.
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movl 0, %eax
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cmpl %eax, %esi
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jnc 3f
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*/
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print_debug("eax and esi: ");
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print_debug_hex32(eax); print_debug(" ");
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print_debug_hex32(esi); print_debug("\r\n");
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if (eax > esi) { /* ??*/
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// This is the current best MA mapping.
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// Save the address and its MA mapping value.
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best = r;
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esi = eax;
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}
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}
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pci_write_config8(north,0x58, raminit_ma_reg_table[best]);
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print_debug("enabled first bank of ram ... ma is ");
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print_debug_hex8(pci_read_config8(north, 0x58));
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print_debug("\r\n");
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}
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}
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base = 0;
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/* runs out of variable space. */
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/* this is unrolled and constants used as much as possible to help
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* us not run out of registers.
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* we'll run out of code space instead :-)
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*/
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// for(i = 0; i < 8; i++)
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base = do_module_size(0); /*, base);*/
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pci_write_config8(north, ramregs[0], base);
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base += do_module_size(1); /*, base);*/
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pci_write_config8(north, ramregs[1], base);
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/* runs out of code space. */
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for(i = 2; i < 8; i++){
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pci_write_config8(north, ramregs[i], base);
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/*
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pci_write_config8(north, ramregs[3], base);
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pci_write_config8(north, ramregs[4], base);
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pci_write_config8(north, ramregs[5], base);
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pci_write_config8(north, ramregs[6], base);
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pci_write_config8(north, ramregs[7], base);
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*/
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for(slot = 0; slot < 4; slot++) {
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size = spd_module_size(slot);
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/* side 0 */
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base += size & 0xffff;
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pci_write_config8(north, ramregs[2*slot], base);
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/* side 1 */
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base += size >> 16;
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if (base > 0xff)
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base = 0xff;
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pci_write_config8(north, ramregs[2*slot + 1], base);
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if (!size)
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continue;
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/* Calculate the value of MA mapping type register,
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* based on size of SDRAM chips. */
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size = (size & 0xffff) << (3 + 3);
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/* convert module size to be in Mbits */
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size /= spd_num_chips(slot);
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print_debug_hex16(size);
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print_debug(" is the chip size\r\n");
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if (size < 64)
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ma = 0;
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if (size < 256)
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ma = 8;
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else
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ma = 0xe;
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print_debug_hex16(ma);
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print_debug(" is the MA type\r\n");
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set_ma_mapping(north, slot, ma);
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}
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/*
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base = do_module_size(0xa0, base);
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base = do_module_size(0xa0, base);
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base = do_module_size(0xa0, base);
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base = do_module_size(0xa0, base);
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base = do_module_size(0xa0, base);
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base = do_module_size(0xa0, base);*/
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print_err("vt8601 done\r\n");
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/*
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dumpnorth(north);
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udelay(1000);
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*/
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}
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@ -94,8 +94,8 @@ romimage "fallback"
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# option ROM_SECTION_SIZE=0x100000
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option LINUXBIOS_EXTRA_VERSION=".0Fallback"
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mainboard arima/hdama
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payload ../../../../tg3--ide_disk.zelf
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# payload ../../../../opteron_phase1_p4_noapic
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# payload ../../../../tg3--ide_disk.zelf
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payload ../../../../opteron_phase1_p4_noapic
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# payload ../../../../../../hdama-1
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# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
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end
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