drivers/intel/fsp2_0: decouple FSP_PEIM_TO_PEIM_INTERFACE from FSP 2.1

Not all FSPs based on FSP 2.1 supports the feature of external PPI
interface pulled in via FSP_PEIM_TO_PEIM_INTERFACE.

Deselect FSP_PEIM_TO_PEIM_INTERFACE when PLATFORM_USES_FSP2_1 is
selected.

Update Kconfig of SOCs affected (icelake, jasperlake, tigerlake).

Change-Id: I5df03f8bcf15c9e05c9fd904a79f740260a3aed7
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>

src/drivers/intel/fsp2_0/Kconfig

@@ -11,12 +11,10 @@ config PLATFORM_USES_FSP2_1
 	default n
 	select PLATFORM_USES_FSP2_0
 	select FSP_USES_CB_STACK
-	select FSP_PEIM_TO_PEIM_INTERFACE
 	help
 	  Include FSP 2.1 wrappers and functionality.
-	  Features added into FSP 2.1 specification that impacts coreboot are:
+	  Feature added into FSP 2.1 specification that impacts coreboot is:
 	  1. Remove FSP stack switch and use the same stack with boot firmware
-	  2. FSP should support external PPI interface pulled in via FSP_PEIM_TO_PEIM_INTERFACE
 
 config PLATFORM_USES_FSP2_2
 	bool

src/soc/intel/common/block/cpu/Kconfig

@@ -61,7 +61,7 @@ config USE_INTEL_FSP_MP_INIT
 config USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI
 	bool "Perform MP Initialization by FSP using coreboot MP PPI service"
 	depends on FSP_USES_MP_SERVICES_PPI
-	default y if PLATFORM_USES_FSP2_1
+	default y if FSP_PEIM_TO_PEIM_INTERFACE
 	default n
 	help
 	  This option allows FSP to make use of MP services PPI published by

src/soc/intel/icelake/Kconfig

@@ -31,6 +31,7 @@ config CPU_SPECIFIC_OPTIONS
 	select PARALLEL_MP_AP_WORK
 	select MICROCODE_BLOB_UNDISCLOSED
 	select PLATFORM_USES_FSP2_1
+	select FSP_PEIM_TO_PEIM_INTERFACE
 	select REG_SCRIPT
 	select SMP
 	select PMC_GLOBAL_RESET_ENABLE_LOCK

src/soc/intel/jasperlake/Kconfig

@@ -33,6 +33,7 @@ config CPU_SPECIFIC_OPTIONS
 	select PARALLEL_MP_AP_WORK
 	select MICROCODE_BLOB_UNDISCLOSED
 	select PLATFORM_USES_FSP2_1
+	select FSP_PEIM_TO_PEIM_INTERFACE
 	select REG_SCRIPT
 	select SMP
 	select PMC_GLOBAL_RESET_ENABLE_LOCK

src/soc/intel/tigerlake/Kconfig

@@ -33,6 +33,7 @@ config CPU_SPECIFIC_OPTIONS
 	select PARALLEL_MP_AP_WORK
 	select MICROCODE_BLOB_UNDISCLOSED
 	select PLATFORM_USES_FSP2_1
+	select FSP_PEIM_TO_PEIM_INTERFACE
 	select REG_SCRIPT
 	select SMP
 	select PMC_GLOBAL_RESET_ENABLE_LOCK