soc/intel/common/block: Provide mmc.c for setting dll registers

Currently, we don't have UPDs to set emmc settings per mainboard on CML.

This code change is to create mmc.c to provide interface to override dll
settings per mainboard.

Notice: set_mmc_dll function will override the dll values in FSP.

BUG=b:131401116
BRANCH=none
TEST=Boot to OS and confirm the dll values have been overridden.

Change-Id: Ib3c72b9851f41585ec099d8ae83a721af87ed383
Signed-off-by: Kane Chen <kane.chen@intel.com>
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/soc/intel/common/block/include/intelblocks/chip.h

@@ -18,6 +18,7 @@
 
 #include <intelblocks/gspi.h>
 #include <drivers/i2c/designware/dw_i2c.h>
+#include <intelblocks/mmc.h>
 
 enum {
 	CHIPSET_LOCKDOWN_FSP = 0, /* FSP handles locking per UPDs */
@@ -35,6 +36,7 @@ struct soc_intel_common_config {
 	struct dw_i2c_bus_config i2c[CONFIG_SOC_INTEL_I2C_DEV_MAX];
 	/* PCH Thermal Trip Temperature in deg C */
 	uint8_t pch_thermal_trip;
+	struct mmc_dll_params emmc_dll;
 };
 
 /* This function to retrieve soc config structure required by common code */

src/soc/intel/common/block/include/intelblocks/mmc.h

@@ -13,17 +13,11 @@
  * GNU General Public License for more details.
  */
 
-#ifndef SOC_INTEL_COMMON_BLOCK_EARLY_MMC_H
+#ifndef SOC_INTEL_COMMON_BLOCK_MMC_H
-#define SOC_INTEL_COMMON_BLOCK_EARLY_MMC_H
+#define SOC_INTEL_COMMON_BLOCK_MMC_H
 
 #include <stdint.h>
 
-/*
- * Following should be defined in soc/iomap.h
- * PRERAM_MMC_BASE_ADDRESS - Provide an address to setup emmc controller's
-			     PCI BAR.
- */
-
 /*
  * Structure for the following delay registers
  * emmc_tx_data_cntl1: Tx Delay Control 1 (Tx_DATA_dly_1)-Offset 824h
@@ -60,8 +54,27 @@ int soc_configure_mmc_gpios(void);
  * returns 0, if able to get register settings; otherwise returns -1
  */
 int soc_get_mmc_dll(struct mmc_dll_params *params);
+/*
+ * Set mmc delay register settings.
+ * bar: eMMC controller MMIO base address.
+ * returns 0, if able to set register settings; otherwise returns -1
+ */
+int set_mmc_dll(void *bar);
+
+#define EMMC_TX_CMD_CNTL_OFFSET			0x820
+#define EMMC_TX_DATA_CNTL1_OFFSET		0x824
+#define EMMC_TX_DATA_CNTL2_OFFSET		0x828
+#define EMMC_RX_CMD_DATA_CNTL1_OFFSET		0x82C
+#define EMMC_RX_STROBE_CNTL_OFFSET		0x830
+#define EMMC_RX_CMD_DATA_CNTL2_OFFSET		0x834
 
 #if CONFIG(SOC_INTEL_COMMON_EARLY_MMC_WAKE)
+/*
+ * Following should be defined in soc/iomap.h
+ * PRERAM_MMC_BASE_ADDRESS - Provide an address to setup emmc controller's
+			PCI BAR.
+ */
+
 /*
  * Initializes sdhci / mmc controller and sends CMD0, CMD1 to emmc card.
  * In case of success: It returns 0 and adds cbmem entry CBMEM_ID_MMC_STATUS
@@ -77,4 +90,4 @@ static inline int early_mmc_wake_hw(void)
 	return -1;
 }
 #endif /* CONFIG_SOC_INTEL_COMMON_EARLY_MMC_WAKE */
-#endif /* SOC_INTEL_COMMON_BLOCK_EARLY_MMC_H */
+#endif /* SOC_INTEL_COMMON_BLOCK_MMC_H */

src/soc/intel/common/block/scs/Kconfig

@@ -12,3 +12,10 @@ config SOC_INTEL_COMMON_EARLY_MMC_WAKE
 	help
 	  Send CMD1 early in romstage to improve boot time. It requires emmc
 	  DLL tuning parameters to be added to devicetree.cb
+
+config SOC_INTEL_COMMON_MMC_OVERRIDE
+	bool
+	default n
+	help
+	  Override the MMC settings after FSP-S.
+	  It should be used only when there is no FSP UPDs for certain setting.

src/soc/intel/common/block/scs/Makefile.inc

@@ -1,2 +1,3 @@
 ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SCS) += sd.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SCS) += mmc.c
 romstage-$(CONFIG_SOC_INTEL_COMMON_EARLY_MMC_WAKE) += early_mmc.c

src/soc/intel/common/block/scs/early_mmc.c

@@ -21,18 +21,11 @@
 #include <compiler.h>
 #include <console/console.h>
 #include <device/pci.h>
-#include <intelblocks/early_mmc.h>
+#include <intelblocks/mmc.h>
 #include <soc/iomap.h>
 #include <soc/pci_devs.h>
 #include <string.h>
 
-#define EMMC_TX_CMD_CNTL_OFFSET			0x820
-#define EMMC_TX_DATA_CNTL1_OFFSET		0x824
-#define EMMC_TX_DATA_CNTL2_OFFSET		0x828
-#define EMMC_RX_CMD_DATA_CNTL1_OFFSET		0x82C
-#define EMMC_RX_STROBE_CNTL_OFFSET		0x830
-#define EMMC_RX_CMD_DATA_CNTL2_OFFSET		0x834
-
 void soc_sd_mmc_controller_quirks(struct sd_mmc_ctrlr *ctrlr)
 {
 	uint32_t f_min, f_max;
@@ -62,32 +55,6 @@ static void disable_mmc_controller_bar(void)
 				~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY));
 }
 
-static int set_mmc_dll(void *ioaddr)
-{
-	struct mmc_dll_params dll_params;
-
-	if (soc_get_mmc_dll(&dll_params) < 0) {
-		printk(BIOS_ERR,
-			"MMC early init: failed to get mmc DLL parameters\n");
-		return -1;
-	}
-
-	write32(ioaddr + EMMC_TX_DATA_CNTL1_OFFSET,
-		dll_params.emmc_tx_data_cntl1);
-	write32(ioaddr + EMMC_TX_DATA_CNTL2_OFFSET,
-		dll_params.emmc_tx_data_cntl2);
-	write32(ioaddr + EMMC_RX_CMD_DATA_CNTL1_OFFSET,
-		dll_params.emmc_rx_cmd_data_cntl1);
-	write32(ioaddr + EMMC_RX_CMD_DATA_CNTL2_OFFSET,
-		dll_params.emmc_rx_cmd_data_cntl2);
-	write32(ioaddr + EMMC_RX_STROBE_CNTL_OFFSET,
-		dll_params.emmc_rx_strobe_cntl);
-	write32(ioaddr + EMMC_TX_CMD_CNTL_OFFSET,
-		dll_params.emmc_tx_cmd_cntl);
-
-	return 0;
-}
-
 static void set_early_mmc_wake_status(int32_t status)
 {
 	int32_t *ms_cbmem;

src/soc/intel/common/block/scs/mmc.c

@@ -0,0 +1,95 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <console/console.h>
+#include <intelblocks/chip.h>
+#include <intelblocks/mmc.h>
+
+static int mmc_write_dll_reg(void *bar, uint32_t reg, uint32_t val)
+{
+	int ret = 0;
+	if (val) {
+		write32(bar + reg, val);
+		ret = 1;
+	}
+	return ret;
+}
+
+int set_mmc_dll(void *bar)
+{
+	const struct soc_intel_common_config *common_config;
+	const struct mmc_dll_params *dll_params;
+	int override = 0;
+
+	common_config = chip_get_common_soc_structure();
+	dll_params = &common_config->emmc_dll;
+
+	override |= mmc_write_dll_reg(bar, EMMC_TX_CMD_CNTL_OFFSET,
+		dll_params->emmc_tx_cmd_cntl);
+
+	override |= mmc_write_dll_reg(bar, EMMC_TX_DATA_CNTL1_OFFSET,
+		dll_params->emmc_tx_data_cntl1);
+
+	override |= mmc_write_dll_reg(bar, EMMC_TX_DATA_CNTL2_OFFSET,
+		dll_params->emmc_tx_data_cntl2);
+
+	override |= mmc_write_dll_reg(bar, EMMC_RX_CMD_DATA_CNTL1_OFFSET,
+		dll_params->emmc_rx_cmd_data_cntl1);
+
+	override |= mmc_write_dll_reg(bar, EMMC_RX_STROBE_CNTL_OFFSET,
+		dll_params->emmc_rx_strobe_cntl);
+
+	override |= mmc_write_dll_reg(bar, EMMC_RX_CMD_DATA_CNTL2_OFFSET,
+		dll_params->emmc_rx_cmd_data_cntl2);
+
+	if (override == 0) {
+		printk(BIOS_INFO, "Skip Emmc dll value programming\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+static void mmc_soc_init(struct device *dev)
+{
+	const struct resource *res;
+
+	if (!CONFIG(SOC_INTEL_COMMON_MMC_OVERRIDE))
+		return;
+
+	res = find_resource(dev, PCI_BASE_ADDRESS_0);
+	set_mmc_dll((void *)(uintptr_t)(res->base));
+}
+
+static struct device_operations dev_ops = {
+	.read_resources			= pci_dev_read_resources,
+	.set_resources			= pci_dev_set_resources,
+	.enable_resources		= pci_dev_enable_resources,
+	.init				= mmc_soc_init,
+	.ops_pci			= &pci_dev_ops_pci,
+};
+
+static const unsigned short pci_device_ids[] = {
+	PCI_DEVICE_ID_INTEL_CMP_EMMC,
+	0
+};
+
+static const struct pci_driver pch_sd __pci_driver = {
+	.ops		= &dev_ops,
+	.vendor		= PCI_VENDOR_ID_INTEL,
+	.devices	= pci_device_ids,
+};