mb/google/volteer: set TcssXhciEn to 1

BUG=144874778
TEST=Built with Volteer recipe and verified USB functionality

Change-Id: I6cbdbd8a4f65a0fe19e3fb8d7b60b8b849f104e7
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Brandon Breitenstein 2020-03-06 10:51:30 -08:00 committed by Patrick Georgi
parent f6f54dd3fa
commit 01ec713c26
1 changed files with 3 additions and 0 deletions

View File

@ -110,6 +110,9 @@ chip soc/intel/tigerlake
[PchSerialIoIndexUART2] = PchSerialIoDisabled,
}"
# TCSS USB3
register "TcssXhciEn" = "1"
# DP port
register "DdiPortAConfig" = "1" # eDP
register "DdiPortBConfig" = "0"