Drop the unfinished, non-working Bitworks IMS board.
It never worked in v2 (the v1 port did work AFAIK, though), and it's not really useful as reference for other boards anymore (as we now have a dozen or so 440BX boards which work in v2). This is a specialized, custom board (not sold on the "public market"), so it's probably not useful for pretty much everyone out there anyway. We can easily re-add it later (based on one of the other 440BX boards) should there be interest and/or someone with the hardware to test. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Jordan Crouse <jordan.crouse@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2988 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
parent
254f47ef98
commit
020724fc70
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@ -1,136 +0,0 @@
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##
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## Compute the location and size of where this firmware image
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## (linuxBIOS plus bootloader) will live in the boot rom chip.
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##
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if USE_FALLBACK_IMAGE
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default ROM_SECTION_SIZE = FALLBACK_SIZE
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default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
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else
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default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
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default ROM_SECTION_OFFSET = 0
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end
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##
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## Compute the start location and size size of
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## The linuxBIOS bootloader.
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##
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default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
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##
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## Compute where this copy of linuxBIOS will start in the boot rom
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##
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default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
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##
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## Compute a range of ROM that can cached to speed up linuxBIOS,
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## execution speed.
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##
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## XIP_ROM_SIZE must be a power of 2.
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## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
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##
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default XIP_ROM_SIZE=65536
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default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
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##
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## Set all of the defaults for an x86 architecture
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##
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arch i386 end
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##
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## Build the objects we have code for in this directory.
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##
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driver mainboard.o
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#if HAVE_PIRQ_TABLE object irq_tables.o end
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#object reset.o
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##
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## Romcc output
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##
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makerule ./failover.E
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depends "$(MAINBOARD)/failover.c ./romcc"
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action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
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end
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makerule ./failover.inc
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depends "$(MAINBOARD)/failover.c ./romcc"
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action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
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end
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makerule ./auto.E
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depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
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action "./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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makerule ./auto.inc
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depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
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action "./romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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##
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## Build our 16 bit and 32 bit linuxBIOS entry code
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##
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mainboardinit cpu/x86/16bit/entry16.inc
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mainboardinit cpu/x86/32bit/entry32.inc
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ldscript /cpu/x86/16bit/entry16.lds
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ldscript /cpu/x86/32bit/entry32.lds
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##
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## Build our reset vector (This is where linuxBIOS is entered)
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##
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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### Should this be in the northbridge code?
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mainboardinit arch/i386/lib/cpu_reset.inc
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##
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## Include an id string (For safe flashing)
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##
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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###
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### This is the early phase of linuxBIOS startup
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### Things are delicate and we test to see if we should
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### failover to another image.
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###
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if USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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mainboardinit ./failover.inc
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end
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###
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### O.k. We aren't just an intermediary anymore!
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###
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##
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## Setup RAM
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##
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mainboardinit cpu/x86/fpu/enable_fpu.inc
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mainboardinit cpu/x86/mmx/enable_mmx.inc
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mainboardinit ./auto.inc
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mainboardinit cpu/x86/mmx/disable_mmx.inc
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##
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## Include the secondary Configuration files
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##
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dir /pc80
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config chip.h
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chip northbridge/intel/i440bx
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device pci_domain 0 on
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end
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chip cpu/intel/socket_PGA370
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end
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end
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@ -1,157 +0,0 @@
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uses HAVE_MP_TABLE
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uses HAVE_PIRQ_TABLE
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uses USE_FALLBACK_IMAGE
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uses HAVE_FALLBACK_BOOT
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uses HAVE_HARD_RESET
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uses HAVE_OPTION_TABLE
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uses USE_OPTION_TABLE
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uses CONFIG_ROM_PAYLOAD
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uses IRQ_SLOT_COUNT
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uses MAINBOARD
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uses MAINBOARD_VENDOR
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uses MAINBOARD_PART_NUMBER
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uses LINUXBIOS_EXTRA_VERSION
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uses ARCH
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uses FALLBACK_SIZE
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uses STACK_SIZE
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uses HEAP_SIZE
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uses ROM_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_IMAGE_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_SECTION_OFFSET
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uses CONFIG_ROM_PAYLOAD_START
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uses CONFIG_COMPRESSED_PAYLOAD_LZMA
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uses PAYLOAD_SIZE
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uses _ROMBASE
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uses _RAMBASE
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uses XIP_ROM_SIZE
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uses XIP_ROM_BASE
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uses HAVE_MP_TABLE
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uses CROSS_COMPILE
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uses CC
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uses HOSTCC
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uses OBJCOPY
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uses DEFAULT_CONSOLE_LOGLEVEL
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uses MAXIMUM_CONSOLE_LOGLEVEL
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uses CONFIG_CONSOLE_SERIAL8250
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uses TTYS0_BAUD
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uses TTYS0_BASE
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uses TTYS0_LCS
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uses CONFIG_UDELAY_TSC
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## ROM_SIZE is the size of boot ROM that this board will use.
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default ROM_SIZE = 512*1024
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###
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### Build options
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###
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##
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## Build code for the fallback boot
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##
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default HAVE_FALLBACK_BOOT=1
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##
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## no MP table
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##
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default HAVE_MP_TABLE=0
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##
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## Build code to reset the motherboard from linuxBIOS
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##
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default HAVE_HARD_RESET=0
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##
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## Build code to export a programmable irq routing table
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##
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default HAVE_PIRQ_TABLE=0
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default IRQ_SLOT_COUNT=4
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#object irq_tables.o
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##
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## Build code to export a CMOS option table
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##
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default HAVE_OPTION_TABLE=0
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###
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### LinuxBIOS layout values
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###
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## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
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default ROM_IMAGE_SIZE = 65536
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default FALLBACK_SIZE = 131072
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##
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## Use a small 8K stack
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##
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default STACK_SIZE=0x2000
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##
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## Use a small 16K heap
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##
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default HEAP_SIZE=0x4000
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##
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## Only use the option table in a normal image
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##
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#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
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default USE_OPTION_TABLE = 0
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default _RAMBASE = 0x00004000
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default CONFIG_ROM_PAYLOAD = 1
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##
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## The default compiler
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##
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default CROSS_COMPILE=""
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default CC="$(CROSS_COMPILE)gcc -m32"
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default HOSTCC="gcc"
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##
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## The Serial Console
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##
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||||
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# To Enable the Serial Console
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default CONFIG_CONSOLE_SERIAL8250=1
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## Select the serial console baud rate
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default TTYS0_BAUD=115200
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#default TTYS0_BAUD=57600
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#default TTYS0_BAUD=38400
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#default TTYS0_BAUD=19200
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#default TTYS0_BAUD=9600
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#default TTYS0_BAUD=4800
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#default TTYS0_BAUD=2400
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#default TTYS0_BAUD=1200
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# Select the serial console base port
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default TTYS0_BASE=0x3f8
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# Select the serial protocol
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# This defaults to 8 data bits, 1 stop bit, and no parity
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default TTYS0_LCS=0x3
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##
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### Select the linuxBIOS loglevel
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##
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## EMERG 1 system is unusable
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## ALERT 2 action must be taken immediately
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## CRIT 3 critical conditions
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||||
## ERR 4 error conditions
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## WARNING 5 warning conditions
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## NOTICE 6 normal but significant condition
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## INFO 7 informational
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## DEBUG 8 debug-level messages
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## SPEW 9 Way too many details
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||||
## Request this level of debugging output
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default DEFAULT_CONSOLE_LOGLEVEL=9
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## At a maximum only compile in this level of debugging
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||||
default MAXIMUM_CONSOLE_LOGLEVEL=9
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||||
default CONFIG_UDELAY_TSC=1
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||||
end
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||||
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@ -1,96 +0,0 @@
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|||
#define ASSEMBLY 1
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|
||||
#include <stdint.h>
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||||
#include <device/pci_def.h>
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||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
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||||
#include <arch/romcc_io.h>
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||||
#include <arch/hlt.h>
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||||
#include "pc80/serial.c"
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||||
#include "arch/i386/lib/console.c"
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||||
#include "ram/ramtest.c"
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#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
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#include "superio/nsc/pc87351/pc87351_early_serial.c"
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||||
#include "northbridge/intel/i440bx/raminit.h"
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#include "cpu/x86/mtrr/earlymtrr.c"
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||||
#include "cpu/x86/bist.h"
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1)
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||||
|
||||
void udelay(int usecs)
|
||||
{
|
||||
int i;
|
||||
for(i = 0; i < usecs; i++)
|
||||
outb(i&0xff, 0x80);
|
||||
}
|
||||
|
||||
#include "debug.c"
|
||||
#include "lib/delay.c"
|
||||
|
||||
static void enable_shadow_ram(void)
|
||||
{
|
||||
uint8_t shadowreg;
|
||||
/* dev 0 for northbridge */
|
||||
shadowreg = pci_read_config8(0, 0x59);
|
||||
/* 0xf0000-0xfffff */
|
||||
shadowreg |= 0x30;
|
||||
pci_write_config8(0, 0x59, shadowreg);
|
||||
}
|
||||
|
||||
static inline int spd_read_byte(unsigned device, unsigned address)
|
||||
{
|
||||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
#include "northbridge/intel/i440bx/raminit.c"
|
||||
#include "northbridge/intel/i440bx/debug.c"
|
||||
#include "sdram/generic_sdram.c"
|
||||
|
||||
static void main(unsigned long bist)
|
||||
{
|
||||
static const struct mem_controller memctrl[] = {
|
||||
{
|
||||
.d0 = PCI_DEV(0, 0, 0),
|
||||
.channel0 = {
|
||||
(0xa << 3) | 0,
|
||||
(0xa << 3) | 1,
|
||||
(0xa << 3) | 2,
|
||||
(0xa << 3) | 3,
|
||||
},
|
||||
}
|
||||
};
|
||||
|
||||
if (bist == 0) {
|
||||
early_mtrr_init();
|
||||
}
|
||||
pc87351_enable_serial(SERIAL_DEV, TTYS0_BASE);
|
||||
uart_init();
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
enable_shadow_ram();
|
||||
|
||||
enable_smbus();
|
||||
|
||||
dump_spd_registers(&memctrl[0]);
|
||||
|
||||
sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl);
|
||||
|
||||
/* Check whether RAM is working.
|
||||
*
|
||||
* Do _not_ check the area from 640 KB - 1 MB, as that's not really
|
||||
* RAM, but rather reserved for various other things:
|
||||
*
|
||||
* - 640 KB - 768 KB: Video Buffer Area
|
||||
* - 768 KB - 896 KB: Expansion Area
|
||||
* - 896 KB - 960 KB: Extended System BIOS Area
|
||||
* - 960 KB - 1 MB: Memory (BIOS Area) - System BIOS Area
|
||||
*
|
||||
* Trying to check these areas will fail.
|
||||
*/
|
||||
/* TODO: This is currently hardcoded to check 64 MB. */
|
||||
ram_check(0x00000000, 0x0009ffff); /* 0 - 640 KB */
|
||||
ram_check(0x00100000, 0x007c0000); /* 1 MB - 64 MB */
|
||||
}
|
||||
|
|
@ -1,5 +0,0 @@
|
|||
extern struct chip_operations mainboard_bitworks_ims_ops;
|
||||
|
||||
struct mainboard_bitworks_ims_config {
|
||||
int nothing;
|
||||
};
|
||||
|
|
@ -1,74 +0,0 @@
|
|||
entries
|
||||
|
||||
#start-bit length config config-ID name
|
||||
#0 8 r 0 seconds
|
||||
#8 8 r 0 alarm_seconds
|
||||
#16 8 r 0 minutes
|
||||
#24 8 r 0 alarm_minutes
|
||||
#32 8 r 0 hours
|
||||
#40 8 r 0 alarm_hours
|
||||
#48 8 r 0 day_of_week
|
||||
#56 8 r 0 day_of_month
|
||||
#64 8 r 0 month
|
||||
#72 8 r 0 year
|
||||
#80 4 r 0 rate_select
|
||||
#84 3 r 0 REF_Clock
|
||||
#87 1 r 0 UIP
|
||||
#88 1 r 0 auto_switch_DST
|
||||
#89 1 r 0 24_hour_mode
|
||||
#90 1 r 0 binary_values_enable
|
||||
#91 1 r 0 square-wave_out_enable
|
||||
#92 1 r 0 update_finished_enable
|
||||
#93 1 r 0 alarm_interrupt_enable
|
||||
#94 1 r 0 periodic_interrupt_enable
|
||||
#95 1 r 0 disable_clock_updates
|
||||
#96 288 r 0 temporary_filler
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
385 1 e 4 last_boot
|
||||
386 1 e 1 ECC_memory
|
||||
388 4 r 0 reboot_bits
|
||||
392 3 e 5 baud_rate
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
416 4 e 7 boot_first
|
||||
420 4 e 7 boot_second
|
||||
424 4 e 7 boot_third
|
||||
428 4 h 0 boot_index
|
||||
432 8 h 0 boot_countdown
|
||||
1008 16 h 0 check_sum
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
5 0 115200
|
||||
5 1 57600
|
||||
5 2 38400
|
||||
5 3 19200
|
||||
5 4 9600
|
||||
5 5 4800
|
||||
5 6 2400
|
||||
5 7 1200
|
||||
6 6 Notice
|
||||
6 7 Info
|
||||
6 8 Debug
|
||||
6 9 Spew
|
||||
7 0 Network
|
||||
7 1 HDD
|
||||
7 2 Floppy
|
||||
7 8 Fallback_Network
|
||||
7 9 Fallback_HDD
|
||||
7 10 Fallback_Floppy
|
||||
#7 3 ROM
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 1007 1008
|
||||
|
||||
|
||||
|
|
@ -1,66 +0,0 @@
|
|||
|
||||
static void print_debug_pci_dev(unsigned dev)
|
||||
{
|
||||
print_debug("PCI: ");
|
||||
print_debug_hex8((dev >> 16) & 0xff);
|
||||
print_debug_char(':');
|
||||
print_debug_hex8((dev >> 11) & 0x1f);
|
||||
print_debug_char('.');
|
||||
print_debug_hex8((dev >> 8) & 7);
|
||||
}
|
||||
|
||||
static void print_pci_devices(void)
|
||||
{
|
||||
device_t dev;
|
||||
for(dev = PCI_DEV(0, 0, 0);
|
||||
dev <= PCI_DEV(0, 0x1f, 0x7);
|
||||
dev += PCI_DEV(0,0,1)) {
|
||||
uint32_t id;
|
||||
id = pci_read_config32(dev, PCI_VENDOR_ID);
|
||||
if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
|
||||
(((id >> 16) & 0xffff) == 0xffff) ||
|
||||
(((id >> 16) & 0xffff) == 0x0000)) {
|
||||
continue;
|
||||
}
|
||||
print_debug_pci_dev(dev);
|
||||
print_debug("\r\n");
|
||||
}
|
||||
}
|
||||
|
||||
static void dump_pci_device(unsigned dev)
|
||||
{
|
||||
int i;
|
||||
print_debug_pci_dev(dev);
|
||||
print_debug("\r\n");
|
||||
|
||||
for(i = 0; i <= 255; i++) {
|
||||
unsigned char val;
|
||||
if ((i & 0x0f) == 0) {
|
||||
print_debug_hex8(i);
|
||||
print_debug_char(':');
|
||||
}
|
||||
val = pci_read_config8(dev, i);
|
||||
print_debug_char(' ');
|
||||
print_debug_hex8(val);
|
||||
if ((i & 0x0f) == 0x0f) {
|
||||
print_debug("\r\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void dump_pci_devices(void)
|
||||
{
|
||||
device_t dev;
|
||||
for(dev = PCI_DEV(0, 0, 0);
|
||||
dev <= PCI_DEV(0, 0x1f, 0x7);
|
||||
dev += PCI_DEV(0,0,1)) {
|
||||
uint32_t id;
|
||||
id = pci_read_config32(dev, PCI_VENDOR_ID);
|
||||
if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
|
||||
(((id >> 16) & 0xffff) == 0xffff) ||
|
||||
(((id >> 16) & 0xffff) == 0x0000)) {
|
||||
continue;
|
||||
}
|
||||
dump_pci_device(dev);
|
||||
}
|
||||
}
|
||||
|
|
@ -1,32 +0,0 @@
|
|||
#define ASSEMBLY 1
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <arch/io.h>
|
||||
#include "arch/romcc_io.h"
|
||||
#include "pc80/mc146818rtc_early.c"
|
||||
|
||||
static unsigned long main(unsigned long bist)
|
||||
{
|
||||
/* This is the primary cpu how should I boot? */
|
||||
if (do_normal_boot()) {
|
||||
goto normal_image;
|
||||
}
|
||||
else {
|
||||
goto fallback_image;
|
||||
}
|
||||
normal_image:
|
||||
asm volatile ("jmp __normal_image"
|
||||
: /* outputs */
|
||||
: "a" (bist) /* inputs */
|
||||
: /* clobbers */
|
||||
);
|
||||
cpu_reset:
|
||||
asm volatile ("jmp __cpu_reset"
|
||||
: /* outputs */
|
||||
: "a"(bist) /* inputs */
|
||||
: /* clobbers */
|
||||
);
|
||||
fallback_image:
|
||||
return bist;
|
||||
}
|
||||
|
|
@ -1,7 +0,0 @@
|
|||
#include <device/device.h>
|
||||
#include "chip.h"
|
||||
|
||||
struct chip_operations mainboard_bitworks_ims_ops = {
|
||||
CHIP_NAME("Bitworks IMS Mainboard")
|
||||
};
|
||||
|
||||
|
|
@ -1,43 +0,0 @@
|
|||
#if 0
|
||||
//#include "arch/romcc_io.h"
|
||||
#include <arch/io.h>
|
||||
|
||||
typedef unsigned device_t;
|
||||
|
||||
#define PCI_DEV(BUS, DEV, FN) ( \
|
||||
(((BUS) & 0xFF) << 16) | \
|
||||
(((DEV) & 0x1f) << 11) | \
|
||||
(((FN) & 0x7) << 8))
|
||||
|
||||
static void pci_write_config8(device_t dev, unsigned where, unsigned char value)
|
||||
{
|
||||
unsigned addr;
|
||||
addr = dev | where;
|
||||
outl(0x80000000 | (addr & ~3), 0xCF8);
|
||||
outb(value, 0xCFC + (addr & 3));
|
||||
}
|
||||
|
||||
static void pci_write_config32(device_t dev, unsigned where, unsigned value)
|
||||
{
|
||||
unsigned addr;
|
||||
addr = dev | where;
|
||||
outl(0x80000000 | (addr & ~3), 0xCF8);
|
||||
outl(value, 0xCFC);
|
||||
}
|
||||
|
||||
static unsigned pci_read_config32(device_t dev, unsigned where)
|
||||
{
|
||||
unsigned addr;
|
||||
addr = dev | where;
|
||||
outl(0x80000000 | (addr & ~3), 0xCF8);
|
||||
return inl(0xCFC);
|
||||
}
|
||||
|
||||
#include "../../../northbridge/amd/amdk8/reset_test.c"
|
||||
|
||||
void hard_reset(void)
|
||||
{
|
||||
set_bios_reset();
|
||||
pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1);
|
||||
}
|
||||
#endif
|
||||
|
|
@ -1,29 +0,0 @@
|
|||
# Config file for the Bitworks ims board
|
||||
# This will make a target directory of ./ims
|
||||
|
||||
target ims
|
||||
mainboard bitworks/ims
|
||||
|
||||
option ROM_SIZE=512*1024
|
||||
|
||||
romimage "normal"
|
||||
option USE_FALLBACK_IMAGE=0
|
||||
option ROM_IMAGE_SIZE=0x10000
|
||||
option LINUXBIOS_EXTRA_VERSION=".0Normal"
|
||||
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
|
||||
# payload ../../../../tg3--ide_disk.zelf
|
||||
# payload ../../../../../lnxieepro100.ebi
|
||||
payload /etc/hosts
|
||||
end
|
||||
|
||||
romimage "fallback"
|
||||
option USE_FALLBACK_IMAGE=1
|
||||
option ROM_IMAGE_SIZE=0x10000
|
||||
option LINUXBIOS_EXTRA_VERSION=".0Fallback"
|
||||
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
|
||||
# payload ../../../../tg3--ide_disk.zelf
|
||||
# payload ../../../../../lnxieepro100.ebia
|
||||
payload /etc/hosts
|
||||
end
|
||||
|
||||
buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
|
||||
Loading…
Reference in New Issue