cpu/x86: Introduce and use `CPU_X86_LAPIC`

With using a Kconfig option to add the x86 LAPIC support code to the
build, there's no need for adding the corresponding directory to subdirs
in the CPU/SoC Makefile. Comparing which CPU/SoC Makefiles added
(cpu/)x86/mtrr and (cpu/)x86/lapic before this and the corresponding
MTRR code selection patch and having verified that all platforms
added the MTRR code on that patch shows that soc/example/min86 and
soc/intel/quark are the only platforms that don't end up selecting the
LAPIC code. So for now the default value of CPU_X86_LAPIC is chosen as y
which gets overridden to n in the Kconfig of the two SoCs mentioned
above.

Change-Id: I6f683ea7ba92c91117017ebc6ad063ec54902b0a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

src/cpu/amd/agesa/family14/Makefile.inc

@@ -7,4 +7,3 @@ ramstage-y += chip_name.c
 ramstage-y += model_14_init.c
 
 subdirs-y += ../../mtrr
-subdirs-y += ../../../x86/lapic

src/cpu/amd/agesa/family15tn/Makefile.inc

@@ -10,4 +10,3 @@ smm-y += udelay.c
 
 subdirs-y += ../../mtrr
 subdirs-y += ../../smm
-subdirs-y += ../../../x86/lapic

src/cpu/amd/agesa/family16kb/Makefile.inc

@@ -7,4 +7,3 @@ ramstage-y += chip_name.c
 ramstage-y += model_16_init.c
 
 subdirs-y += ../../mtrr
-subdirs-y += ../../../x86/lapic

src/cpu/amd/pi/00730F01/Makefile.inc

@@ -8,4 +8,3 @@ ramstage-y += model_16_init.c
 ramstage-y += update_microcode.c
 
 subdirs-y += ../../mtrr
-subdirs-y += ../../../x86/lapic

src/cpu/intel/haswell/Makefile.inc

@@ -15,7 +15,6 @@ bootblock-y += bootblock.c
 
 postcar-y += ../car/non-evict/exit_car.S
 
-subdirs-y += ../../x86/lapic
 subdirs-y += ../microcode
 subdirs-y += ../turbo
 

src/cpu/intel/model_2065x/Makefile.inc

@@ -1,6 +1,5 @@
 ramstage-y += model_2065x_init.c
 subdirs-y += ../../x86/name
-subdirs-y += ../../x86/lapic
 subdirs-y += ../../intel/turbo
 subdirs-y += ../../intel/microcode
 subdirs-y += ../smm/gen1

src/cpu/intel/model_206ax/Makefile.inc

@@ -2,7 +2,6 @@ ramstage-y += model_206ax_init.c
 subdirs-y += ../../x86/name
 subdirs-y += ../smm/gen1
 
-subdirs-y += ../../x86/lapic
 subdirs-y += ../microcode
 subdirs-y += ../turbo
 

src/cpu/intel/slot_1/Makefile.inc

@@ -7,7 +7,6 @@ subdirs-y += ../model_65x
 subdirs-y += ../model_67x
 subdirs-y += ../model_68x
 subdirs-y += ../model_6bx
-subdirs-y += ../../x86/lapic
 subdirs-y += ../microcode
 
 bootblock-y += ../car/p3/cache_as_ram.S

src/cpu/intel/socket_441/Makefile.inc

@@ -1,5 +1,4 @@
 subdirs-y += ../model_106cx
-subdirs-y += ../../x86/lapic
 subdirs-y += ../microcode
 subdirs-y += ../speedstep
 

src/cpu/intel/socket_BGA956/Makefile.inc

@@ -1,5 +1,4 @@
 subdirs-y += ../model_1067x
-subdirs-y += ../../x86/lapic
 subdirs-y += ../microcode
 subdirs-y += ../speedstep
 

src/cpu/intel/socket_FCBGA559/Makefile.inc

@@ -1,5 +1,4 @@
 subdirs-y += ../model_106cx
-subdirs-y += ../../x86/lapic
 subdirs-y += ../microcode
 subdirs-y += ../speedstep
 

src/cpu/intel/socket_LGA775/Makefile.inc

@@ -2,7 +2,6 @@ subdirs-y += ../model_6fx
 subdirs-y += ../model_f3x
 subdirs-y += ../model_f4x
 subdirs-y += ../model_1067x
-subdirs-y += ../../x86/lapic
 subdirs-y += ../microcode
 subdirs-y += ../speedstep
 

src/cpu/qemu-x86/Makefile.inc

@@ -6,5 +6,3 @@ bootblock-y += bootblock.c
 romstage-y += ../intel/car/romstage.c
 
 ramstage-y += qemu.c
-
-subdirs-y += ../x86/lapic

src/cpu/x86/Kconfig

@@ -4,6 +4,10 @@ config CPU_X86_CACHE_HELPER
 	help
 	  Add the x86_enable_cache ramstage helper function to the build.
 
+config CPU_X86_LAPIC
+	bool
+	default y
+
 config PARALLEL_MP
 	def_bool y
 	depends on !LEGACY_SMP_INIT

src/cpu/x86/Makefile.inc

@@ -1,4 +1,5 @@
 subdirs-$(CONFIG_CPU_X86_CACHE_HELPER) += cache
+subdirs-$(CONFIG_CPU_X86_LAPIC) += lapic
 subdirs-y += mtrr
 subdirs-y += pae
 subdirs-$(CONFIG_HAVE_SMI_HANDLER) += smm

src/soc/amd/cezanne/Makefile.inc

@@ -2,8 +2,6 @@
 
 ifeq ($(CONFIG_SOC_AMD_CEZANNE),y)
 
-subdirs-y += ../../../cpu/x86/lapic
-
 subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage
 
 # Beware that all-y also adds the compilation unit to verstage on PSP

src/soc/amd/picasso/Makefile.inc

@@ -2,7 +2,6 @@
 
 ifeq ($(CONFIG_SOC_AMD_PICASSO),y)
 
-subdirs-y += ../../../cpu/x86/lapic
 subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage
 subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../common/psp_verstage
 

src/soc/amd/stoneyridge/Makefile.inc

@@ -3,7 +3,6 @@
 ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE),y)
 
 subdirs-y += ../../../cpu/amd/mtrr/
-subdirs-y += ../../../cpu/x86/lapic
 
 bootblock-y += uart.c
 bootblock-y += BiosCallOuts.c

src/soc/example/min86/Kconfig

@@ -19,6 +19,10 @@ config SOC_SPECIFIC_OPTIONS
 	select NO_MMCONF_SUPPORT
 	select UNKNOWN_TSC_RATE
 
+config CPU_X86_LAPIC
+	bool
+	default n
+
 config DCACHE_BSP_STACK_SIZE		# required by arch/x86/car.ld
 	default 0x100
 

src/soc/intel/alderlake/Makefile.inc

@@ -2,7 +2,6 @@ ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE),y)
 subdirs-y += romstage
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
-subdirs-y += ../../../cpu/x86/lapic
 
 # all (bootblock, verstage, romstage, postcar, ramstage)
 all-y += gspi.c

src/soc/intel/apollolake/Makefile.inc

@@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_INTEL_APOLLOLAKE),y)
 subdirs-y += ../../../cpu/intel/common
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
-subdirs-y += ../../../cpu/x86/lapic
 
 bootblock-y += bootblock/bootblock.c
 bootblock-y += ../common/block/cpu/pm_timer_emulation.c

src/soc/intel/baytrail/Makefile.inc

@@ -1,7 +1,6 @@
 ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y)
 
 subdirs-y += romstage
-subdirs-y += ../../../cpu/x86/lapic
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
 subdirs-y += ../../../cpu/intel/common

src/soc/intel/braswell/Makefile.inc

@@ -1,7 +1,6 @@
 ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y)
 
 subdirs-y += romstage
-subdirs-y += ../../../cpu/x86/lapic
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
 subdirs-y += ../../../cpu/intel/common

src/soc/intel/cannonlake/Makefile.inc

@@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE_BASE),y)
 subdirs-y += romstage
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
-subdirs-y += ../../../cpu/x86/lapic
 subdirs-y += ../../../cpu/intel/common
 
 bootblock-y += bootblock/bootblock.c

src/soc/intel/denverton_ns/Makefile.inc

@@ -4,7 +4,6 @@ ifeq ($(CONFIG_SOC_INTEL_DENVERTON_NS),y)
 
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
-subdirs-y += ../../../cpu/x86/lapic
 
 bootblock-y += bootblock/bootblock.c
 bootblock-y += spi.c

src/soc/intel/elkhartlake/Makefile.inc

@@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_INTEL_ELKHARTLAKE),y)
 subdirs-y += romstage
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
-subdirs-y += ../../../cpu/x86/lapic
 
 # all (bootblock, verstage, romstage, postcar, ramstage)
 all-y += gspi.c

src/soc/intel/icelake/Makefile.inc

@@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_INTEL_ICELAKE),y)
 subdirs-y += romstage
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
-subdirs-y += ../../../cpu/x86/lapic
 
 # all (bootblock, verstage, romstage, postcar, ramstage)
 all-y += gspi.c

src/soc/intel/jasperlake/Makefile.inc

@@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_INTEL_JASPERLAKE),y)
 subdirs-y += romstage
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
-subdirs-y += ../../../cpu/x86/lapic
 
 # all (bootblock, verstage, romstage, postcar, ramstage)
 all-y += gspi.c

src/soc/intel/quark/Kconfig

@@ -24,6 +24,10 @@ config CPU_SPECIFIC_OPTIONS
 	select USE_MARCH_586
 	select NO_SMM
 
+config CPU_X86_LAPIC
+	bool
+	default n
+
 #####
 # Debug serial output
 #     The following options configure the debug serial port

src/soc/intel/skylake/Makefile.inc

@@ -5,7 +5,6 @@ subdirs-y += romstage
 subdirs-y += ../../../cpu/intel/common
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
-subdirs-y += ../../../cpu/x86/lapic
 
 bootblock-y += bootblock/bootblock.c
 bootblock-y += i2c.c

src/soc/intel/tigerlake/Makefile.inc

@@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE),y)
 subdirs-y += romstage
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
-subdirs-y += ../../../cpu/x86/lapic
 
 # all (bootblock, verstage, romstage, postcar, ramstage)
 all-y += gspi.c

src/soc/intel/xeon_sp/cpx/Makefile.inc

@@ -3,7 +3,6 @@
 ifeq ($(CONFIG_SOC_INTEL_COOPERLAKE_SP),y)
 
 subdirs-y += ../../../../cpu/intel/turbo
-subdirs-y += ../../../../cpu/x86/lapic
 subdirs-y += ../../../../cpu/intel/microcode
 
 romstage-y += romstage.c ddr.c

src/soc/intel/xeon_sp/skx/Makefile.inc

@@ -4,7 +4,6 @@ ifeq ($(CONFIG_SOC_INTEL_SKYLAKE_SP),y)
 
 subdirs-y += ../../../../cpu/intel/microcode
 subdirs-y += ../../../../cpu/intel/turbo
-subdirs-y += ../../../../cpu/x86/lapic
 
 postcar-y += soc_util.c