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cpu/x86: Introduce and use `CPU_X86_LAPIC` 

With using a Kconfig option to add the x86 LAPIC support code to the
build, there's no need for adding the corresponding directory to subdirs
in the CPU/SoC Makefile. Comparing which CPU/SoC Makefiles added
(cpu/)x86/mtrr and (cpu/)x86/lapic before this and the corresponding
MTRR code selection patch and having verified that all platforms
added the MTRR code on that patch shows that soc/example/min86 and
soc/intel/quark are the only platforms that don't end up selecting the
LAPIC code. So for now the default value of CPU_X86_LAPIC is chosen as y
which gets overridden to n in the Kconfig of the two SoCs mentioned
above.

Change-Id: I6f683ea7ba92c91117017ebc6ad063ec54902b0a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Felix Held 2021-10-23 00:34:43 +02:00 committed by Felix Held
parent 71dfa82380
commit 02164027b2
33 changed files with 13 additions and 31 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/cpu/amd/agesa/family14/Makefile.inc
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@ -7,4 +7,3 @@ ramstage-y += chip_name.c
ramstage-y += model_14_init.c ramstage-y += model_14_init.c
subdirs-y += ../../mtrr subdirs-y += ../../mtrr
subdirs-y += ../../../x86/lapic

1
src/cpu/amd/agesa/family15tn/Makefile.inc
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@ -10,4 +10,3 @@ smm-y += udelay.c
subdirs-y += ../../mtrr subdirs-y += ../../mtrr
subdirs-y += ../../smm subdirs-y += ../../smm
subdirs-y += ../../../x86/lapic

1
src/cpu/amd/agesa/family16kb/Makefile.inc
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@ -7,4 +7,3 @@ ramstage-y += chip_name.c
ramstage-y += model_16_init.c ramstage-y += model_16_init.c
subdirs-y += ../../mtrr subdirs-y += ../../mtrr
subdirs-y += ../../../x86/lapic

1
src/cpu/amd/pi/00730F01/Makefile.inc
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@ -8,4 +8,3 @@ ramstage-y += model_16_init.c
ramstage-y += update_microcode.c ramstage-y += update_microcode.c
subdirs-y += ../../mtrr subdirs-y += ../../mtrr
subdirs-y += ../../../x86/lapic

1
src/cpu/intel/haswell/Makefile.inc
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@ -15,7 +15,6 @@ bootblock-y += bootblock.c
postcar-y += ../car/non-evict/exit_car.S postcar-y += ../car/non-evict/exit_car.S
subdirs-y += ../../x86/lapic
subdirs-y += ../microcode subdirs-y += ../microcode
subdirs-y += ../turbo subdirs-y += ../turbo

1
src/cpu/intel/model_2065x/Makefile.inc
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@ -1,6 +1,5 @@
ramstage-y += model_2065x_init.c ramstage-y += model_2065x_init.c
subdirs-y += ../../x86/name subdirs-y += ../../x86/name
subdirs-y += ../../x86/lapic
subdirs-y += ../../intel/turbo subdirs-y += ../../intel/turbo
subdirs-y += ../../intel/microcode subdirs-y += ../../intel/microcode
subdirs-y += ../smm/gen1 subdirs-y += ../smm/gen1

1
src/cpu/intel/model_206ax/Makefile.inc
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@ -2,7 +2,6 @@ ramstage-y += model_206ax_init.c
subdirs-y += ../../x86/name subdirs-y += ../../x86/name
subdirs-y += ../smm/gen1 subdirs-y += ../smm/gen1
subdirs-y += ../../x86/lapic
subdirs-y += ../microcode subdirs-y += ../microcode
subdirs-y += ../turbo subdirs-y += ../turbo

1
src/cpu/intel/slot_1/Makefile.inc
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@ -7,7 +7,6 @@ subdirs-y += ../model_65x
subdirs-y += ../model_67x subdirs-y += ../model_67x
subdirs-y += ../model_68x subdirs-y += ../model_68x
subdirs-y += ../model_6bx subdirs-y += ../model_6bx
subdirs-y += ../../x86/lapic
subdirs-y += ../microcode subdirs-y += ../microcode
bootblock-y += ../car/p3/cache_as_ram.S bootblock-y += ../car/p3/cache_as_ram.S

1
src/cpu/intel/socket_441/Makefile.inc
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@ -1,5 +1,4 @@
subdirs-y += ../model_106cx subdirs-y += ../model_106cx
subdirs-y += ../../x86/lapic
subdirs-y += ../microcode subdirs-y += ../microcode
subdirs-y += ../speedstep subdirs-y += ../speedstep

1
src/cpu/intel/socket_BGA956/Makefile.inc
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@ -1,5 +1,4 @@
subdirs-y += ../model_1067x subdirs-y += ../model_1067x
subdirs-y += ../../x86/lapic
subdirs-y += ../microcode subdirs-y += ../microcode
subdirs-y += ../speedstep subdirs-y += ../speedstep

1
src/cpu/intel/socket_FCBGA559/Makefile.inc
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@ -1,5 +1,4 @@
subdirs-y += ../model_106cx subdirs-y += ../model_106cx
subdirs-y += ../../x86/lapic
subdirs-y += ../microcode subdirs-y += ../microcode
subdirs-y += ../speedstep subdirs-y += ../speedstep

1
src/cpu/intel/socket_LGA775/Makefile.inc
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@ -2,7 +2,6 @@ subdirs-y += ../model_6fx
subdirs-y += ../model_f3x subdirs-y += ../model_f3x
subdirs-y += ../model_f4x subdirs-y += ../model_f4x
subdirs-y += ../model_1067x subdirs-y += ../model_1067x
subdirs-y += ../../x86/lapic
subdirs-y += ../microcode subdirs-y += ../microcode
subdirs-y += ../speedstep subdirs-y += ../speedstep

2
src/cpu/qemu-x86/Makefile.inc
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@ -6,5 +6,3 @@ bootblock-y += bootblock.c
romstage-y += ../intel/car/romstage.c romstage-y += ../intel/car/romstage.c
ramstage-y += qemu.c ramstage-y += qemu.c
subdirs-y += ../x86/lapic

4
src/cpu/x86/Kconfig
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@ -4,6 +4,10 @@ config CPU_X86_CACHE_HELPER
help help
Add the x86_enable_cache ramstage helper function to the build. Add the x86_enable_cache ramstage helper function to the build.
config CPU_X86_LAPIC
bool
default y
config PARALLEL_MP config PARALLEL_MP
def_bool y def_bool y
depends on !LEGACY_SMP_INIT depends on !LEGACY_SMP_INIT

1
src/cpu/x86/Makefile.inc
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@ -1,4 +1,5 @@
subdirs-$(CONFIG_CPU_X86_CACHE_HELPER) += cache subdirs-$(CONFIG_CPU_X86_CACHE_HELPER) += cache
subdirs-$(CONFIG_CPU_X86_LAPIC) += lapic
subdirs-y += mtrr subdirs-y += mtrr
subdirs-y += pae subdirs-y += pae
subdirs-$(CONFIG_HAVE_SMI_HANDLER) += smm subdirs-$(CONFIG_HAVE_SMI_HANDLER) += smm

2
src/soc/amd/cezanne/Makefile.inc
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@ -2,8 +2,6 @@
ifeq ($(CONFIG_SOC_AMD_CEZANNE),y) ifeq ($(CONFIG_SOC_AMD_CEZANNE),y)
subdirs-y += ../../../cpu/x86/lapic
subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage
# Beware that all-y also adds the compilation unit to verstage on PSP # Beware that all-y also adds the compilation unit to verstage on PSP

1
src/soc/amd/picasso/Makefile.inc
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@ -2,7 +2,6 @@
ifeq ($(CONFIG_SOC_AMD_PICASSO),y) ifeq ($(CONFIG_SOC_AMD_PICASSO),y)
subdirs-y += ../../../cpu/x86/lapic
subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage
subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../common/psp_verstage subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../common/psp_verstage

1
src/soc/amd/stoneyridge/Makefile.inc
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@ -3,7 +3,6 @@
ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE),y) ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE),y)
subdirs-y += ../../../cpu/amd/mtrr/ subdirs-y += ../../../cpu/amd/mtrr/
subdirs-y += ../../../cpu/x86/lapic
bootblock-y += uart.c bootblock-y += uart.c
bootblock-y += BiosCallOuts.c bootblock-y += BiosCallOuts.c

4
src/soc/example/min86/Kconfig
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@ -19,6 +19,10 @@ config SOC_SPECIFIC_OPTIONS
select NO_MMCONF_SUPPORT select NO_MMCONF_SUPPORT
select UNKNOWN_TSC_RATE select UNKNOWN_TSC_RATE
config CPU_X86_LAPIC
bool
default n
config DCACHE_BSP_STACK_SIZE # required by arch/x86/car.ld config DCACHE_BSP_STACK_SIZE # required by arch/x86/car.ld
default 0x100 default 0x100

1
src/soc/intel/alderlake/Makefile.inc
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@ -2,7 +2,6 @@ ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE),y)
subdirs-y += romstage subdirs-y += romstage
subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/microcode
subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/turbo
subdirs-y += ../../../cpu/x86/lapic
# all (bootblock, verstage, romstage, postcar, ramstage) # all (bootblock, verstage, romstage, postcar, ramstage)
all-y += gspi.c all-y += gspi.c

1
src/soc/intel/apollolake/Makefile.inc
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@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_INTEL_APOLLOLAKE),y)
subdirs-y += ../../../cpu/intel/common subdirs-y += ../../../cpu/intel/common
subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/microcode
subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/turbo
subdirs-y += ../../../cpu/x86/lapic
bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/bootblock.c
bootblock-y += ../common/block/cpu/pm_timer_emulation.c bootblock-y += ../common/block/cpu/pm_timer_emulation.c

1
src/soc/intel/baytrail/Makefile.inc
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@ -1,7 +1,6 @@
ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y) ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y)
subdirs-y += romstage subdirs-y += romstage
subdirs-y += ../../../cpu/x86/lapic
subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/microcode
subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/turbo
subdirs-y += ../../../cpu/intel/common subdirs-y += ../../../cpu/intel/common

1
src/soc/intel/braswell/Makefile.inc
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@ -1,7 +1,6 @@
ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y) ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y)
subdirs-y += romstage subdirs-y += romstage
subdirs-y += ../../../cpu/x86/lapic
subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/microcode
subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/turbo
subdirs-y += ../../../cpu/intel/common subdirs-y += ../../../cpu/intel/common

1
src/soc/intel/cannonlake/Makefile.inc
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@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE_BASE),y)
subdirs-y += romstage subdirs-y += romstage
subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/microcode
subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/turbo
subdirs-y += ../../../cpu/x86/lapic
subdirs-y += ../../../cpu/intel/common subdirs-y += ../../../cpu/intel/common
bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/bootblock.c

1
src/soc/intel/denverton_ns/Makefile.inc
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@ -4,7 +4,6 @@ ifeq ($(CONFIG_SOC_INTEL_DENVERTON_NS),y)
subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/microcode
subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/turbo
subdirs-y += ../../../cpu/x86/lapic
bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/bootblock.c
bootblock-y += spi.c bootblock-y += spi.c

1
src/soc/intel/elkhartlake/Makefile.inc
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@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_INTEL_ELKHARTLAKE),y)
subdirs-y += romstage subdirs-y += romstage
subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/microcode
subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/turbo
subdirs-y += ../../../cpu/x86/lapic
# all (bootblock, verstage, romstage, postcar, ramstage) # all (bootblock, verstage, romstage, postcar, ramstage)
all-y += gspi.c all-y += gspi.c

1
src/soc/intel/icelake/Makefile.inc
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@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_INTEL_ICELAKE),y)
subdirs-y += romstage subdirs-y += romstage
subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/microcode
subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/turbo
subdirs-y += ../../../cpu/x86/lapic
# all (bootblock, verstage, romstage, postcar, ramstage) # all (bootblock, verstage, romstage, postcar, ramstage)
all-y += gspi.c all-y += gspi.c

1
src/soc/intel/jasperlake/Makefile.inc
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@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_INTEL_JASPERLAKE),y)
subdirs-y += romstage subdirs-y += romstage
subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/microcode
subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/turbo
subdirs-y += ../../../cpu/x86/lapic
# all (bootblock, verstage, romstage, postcar, ramstage) # all (bootblock, verstage, romstage, postcar, ramstage)
all-y += gspi.c all-y += gspi.c

4
src/soc/intel/quark/Kconfig
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@ -24,6 +24,10 @@ config CPU_SPECIFIC_OPTIONS
select USE_MARCH_586 select USE_MARCH_586
select NO_SMM select NO_SMM
config CPU_X86_LAPIC
bool
default n
##### #####
# Debug serial output # Debug serial output
# The following options configure the debug serial port # The following options configure the debug serial port

1
src/soc/intel/skylake/Makefile.inc
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@ -5,7 +5,6 @@ subdirs-y += romstage
subdirs-y += ../../../cpu/intel/common subdirs-y += ../../../cpu/intel/common
subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/microcode
subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/turbo
subdirs-y += ../../../cpu/x86/lapic
bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/bootblock.c
bootblock-y += i2c.c bootblock-y += i2c.c

1
src/soc/intel/tigerlake/Makefile.inc
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@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE),y)
subdirs-y += romstage subdirs-y += romstage
subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/microcode
subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/turbo
subdirs-y += ../../../cpu/x86/lapic
# all (bootblock, verstage, romstage, postcar, ramstage) # all (bootblock, verstage, romstage, postcar, ramstage)
all-y += gspi.c all-y += gspi.c

1
src/soc/intel/xeon_sp/cpx/Makefile.inc
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@ -3,7 +3,6 @@
ifeq ($(CONFIG_SOC_INTEL_COOPERLAKE_SP),y) ifeq ($(CONFIG_SOC_INTEL_COOPERLAKE_SP),y)
subdirs-y += ../../../../cpu/intel/turbo subdirs-y += ../../../../cpu/intel/turbo
subdirs-y += ../../../../cpu/x86/lapic
subdirs-y += ../../../../cpu/intel/microcode subdirs-y += ../../../../cpu/intel/microcode
romstage-y += romstage.c ddr.c romstage-y += romstage.c ddr.c

1
src/soc/intel/xeon_sp/skx/Makefile.inc
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@ -4,7 +4,6 @@ ifeq ($(CONFIG_SOC_INTEL_SKYLAKE_SP),y)
subdirs-y += ../../../../cpu/intel/microcode subdirs-y += ../../../../cpu/intel/microcode
subdirs-y += ../../../../cpu/intel/turbo subdirs-y += ../../../../cpu/intel/turbo
subdirs-y += ../../../../cpu/x86/lapic
postcar-y += soc_util.c postcar-y += soc_util.c