mediatek/mt8183: Init PLLs for DRAM
Set up DRAM related PLLs. And update post divider table to fulfill all freqency settings. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Ic197cef7d31f75ffe4e7d9e73c9cc544719943ab Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Reviewed-on: https://review.coreboot.org/28667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com>
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@ -255,6 +255,7 @@ enum {
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TVDPLL_HZ = 594 * MHz,
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TVDPLL_HZ = 594 * MHz,
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APLL1_HZ = 180633600,
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APLL1_HZ = 180633600,
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APLL2_HZ = 196608 * KHz,
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APLL2_HZ = 196608 * KHz,
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MPLL_HZ = 208 * MHz,
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};
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};
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/* top_div rate */
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/* top_div rate */
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@ -208,15 +208,16 @@ enum pll_id {
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APMIXED_TVDPLL,
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APMIXED_TVDPLL,
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APMIXED_APLL1,
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APMIXED_APLL1,
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APMIXED_APLL2,
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APMIXED_APLL2,
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APMIXED_NR_PLL
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APMIXED_MPLL,
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APMIXED_PLL_MAX
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};
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};
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const u32 pll_div_rate[] = {
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const u32 pll_div_rate[] = {
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3800UL * MHz,
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3800UL * MHz,
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1248 * MHz,
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1900 * MHz,
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624 * MHz,
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950 * MHz,
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384 * MHz,
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475 * MHz,
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200 * MHz,
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237500 * KHz,
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0,
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0,
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};
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};
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@ -254,6 +255,9 @@ static const struct pll plls[] = {
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PLL(APMIXED_APLL2, apll2_con0, apll2_pwr_con0,
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PLL(APMIXED_APLL2, apll2_con0, apll2_pwr_con0,
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NO_RSTB_SHIFT, 32, apll2_con0, 1, apll2_con1, 0,
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NO_RSTB_SHIFT, 32, apll2_con0, 1, apll2_con1, 0,
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pll_div_rate),
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pll_div_rate),
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PLL(APMIXED_MPLL, mpll_con0, mpll_pwr_con0,
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NO_RSTB_SHIFT, 22, mpll_con1, 24, mpll_con1, 0,
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pll_div_rate),
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};
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};
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struct rate {
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struct rate {
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@ -273,6 +277,7 @@ static const struct rate rates[] = {
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{ .id = APMIXED_TVDPLL, .rate = TVDPLL_HZ },
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{ .id = APMIXED_TVDPLL, .rate = TVDPLL_HZ },
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{ .id = APMIXED_APLL1, .rate = APLL1_HZ },
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{ .id = APMIXED_APLL1, .rate = APLL1_HZ },
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{ .id = APMIXED_APLL2, .rate = APLL2_HZ },
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{ .id = APMIXED_APLL2, .rate = APLL2_HZ },
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{ .id = APMIXED_MPLL, .rate = MPLL_HZ },
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};
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};
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void pll_set_pcw_change(const struct pll *pll)
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void pll_set_pcw_change(const struct pll *pll)
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@ -291,13 +296,13 @@ void mt_pll_init(void)
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setbits_le32(&mtk_apmixed->ap_pll_con0, 0x2);
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setbits_le32(&mtk_apmixed->ap_pll_con0, 0x2);
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/* xPLL PWR ON */
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/* xPLL PWR ON */
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for (i = 0; i < APMIXED_NR_PLL; i++)
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for (i = 0; i < APMIXED_PLL_MAX; i++)
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setbits_le32(plls[i].pwr_reg, PLL_PWR_ON);
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setbits_le32(plls[i].pwr_reg, PLL_PWR_ON);
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udelay(PLL_PWR_ON_DELAY);
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udelay(PLL_PWR_ON_DELAY);
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/* xPLL ISO Disable */
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/* xPLL ISO Disable */
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for (i = 0; i < APMIXED_NR_PLL; i++)
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for (i = 0; i < APMIXED_PLL_MAX; i++)
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clrbits_le32(plls[i].pwr_reg, PLL_ISO);
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clrbits_le32(plls[i].pwr_reg, PLL_ISO);
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udelay(PLL_ISO_DELAY);
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udelay(PLL_ISO_DELAY);
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@ -313,14 +318,14 @@ void mt_pll_init(void)
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read32(&mtk_apmixed->apll2_con1) + 1);
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read32(&mtk_apmixed->apll2_con1) + 1);
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/* xPLL Frequency Enable */
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/* xPLL Frequency Enable */
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for (i = 0; i < APMIXED_NR_PLL; i++)
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for (i = 0; i < APMIXED_PLL_MAX; i++)
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setbits_le32(plls[i].reg, PLL_EN);
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setbits_le32(plls[i].reg, PLL_EN);
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/* wait for PLL stable */
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/* wait for PLL stable */
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udelay(PLL_EN_DELAY);
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udelay(PLL_EN_DELAY);
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/* xPLL DIV RSTB */
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/* xPLL DIV RSTB */
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for (i = 0; i < APMIXED_NR_PLL; i++) {
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for (i = 0; i < APMIXED_PLL_MAX; i++) {
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if (plls[i].rstb_shift != NO_RSTB_SHIFT)
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if (plls[i].rstb_shift != NO_RSTB_SHIFT)
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setbits_le32(plls[i].reg, 1 << plls[i].rstb_shift);
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setbits_le32(plls[i].reg, 1 << plls[i].rstb_shift);
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}
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}
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