mb/starlabs/starbook/cml: Use chipset dt reference names
Use the references from the chipset devicetree as this makes the comments superfluous. Change-Id: Ia004de6606a1685822d5567123887c60d89e3119 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
This commit is contained in:
Felix Singer
Felix Singer
parent
2a4e18ae84
commit
023846e2a2
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@ -53,15 +53,15 @@ chip soc/intel/cannonlake
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device cpu_cluster 0 on end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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device pci 04.0 on # SA Thermal Device
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device ref system_agent on end
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device ref igpu on end
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device ref dptf on
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register "Device4Enable" = "1"
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end
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device pci 12.0 off end # Thermal Subsystem
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device pci 12.5 off end # UFS SCS
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device pci 12.6 off end # GSPI #2
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device pci 14.0 on # USB xHCI
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device ref thermal off end
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device ref ufs off end
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device ref gspi2 off end
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device ref xhci on
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# Motherboard USB Type C
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register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"
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@ -83,16 +83,16 @@ chip soc/intel/cannonlake
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# Internal Bluetooth
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register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"
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end
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device pci 14.1 off end # USB xDCI (OTG)
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device pci 14.2 on end # SRAM
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device pci 14.3 on # CNVi
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device ref xdci off end
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device ref shared_sram on end
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device ref cnvi_wifi on
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chip drivers/wifi/generic
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register "wake" = "GPE0_PME_B0"
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device generic 0 on end
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end
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end
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device pci 14.5 off end # SDCard
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device pci 15.0 on # I2C0
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device ref sdxc off end
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device ref i2c0 on
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chip drivers/i2c/hid
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register "generic.hid" = ""STAR0001""
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register "generic.desc" = ""Touchpad""
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@ -102,34 +102,34 @@ chip soc/intel/cannonlake
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device i2c 2c on end
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end
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end
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device pci 15.1 off end # I2C1
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device pci 15.2 off end # I2C2
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device pci 15.3 off end # I2C3
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.4 off end # Management Engine Interface 3
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device pci 16.5 off end # Management Engine Interface 4
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device pci 17.0 on # SATA
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device ref i2c1 off end
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device ref i2c2 off end
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device ref i2c3 off end
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device ref heci1 on end
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device ref heci2 off end
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device ref csme_ider off end
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device ref csme_ktr off end
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device ref heci3 off end
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device ref heci4 off end
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device ref sata on
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register "SataSalpSupport" = "1"
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# Port 1
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register "SataPortsEnable[1]" = "1"
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register "SataPortsDevSlp[1]" = "1"
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end
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device pci 19.0 on end # I2C4
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device pci 19.1 off end # I2C5
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device pci 19.2 on end # UART #2
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device pci 1a.0 off end # eMMC
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device pci 1c.0 off end # PCI Express Port 1
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device pci 1c.1 off end # PCI Express Port 2
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device pci 1c.2 off end # PCI Express Port 3
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device pci 1c.3 off end # PCI Express Port 4
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device pci 1c.4 off end # PCI Express Port 5
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device pci 1c.5 off end # PCI Express Port 6
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device pci 1c.6 off end # PCI Express Port 7
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device pci 1c.7 off end # PCI Express Port 8
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device pci 1d.0 on # PCI Express Port 9 (SSD x4)
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device ref i2c4 on end
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device ref i2c5 off end
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device ref uart2 on end
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device ref emmc off end
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device ref pcie_rp1 off end
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device ref pcie_rp2 off end
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device ref pcie_rp3 off end
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device ref pcie_rp4 off end
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device ref pcie_rp5 off end
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device ref pcie_rp6 off end
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device ref pcie_rp7 off end
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device ref pcie_rp8 off end
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device ref pcie_rp9 on # SSD x4
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register "PcieRpSlotImplemented[8]" = "1"
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register "PcieRpEnable[8]" = "1"
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register "PcieRpLtrEnable[8]" = "1"
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@ -137,14 +137,14 @@ chip soc/intel/cannonlake
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register "PcieClkSrcClkReq[1]" = "1"
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smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
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end
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device pci 1d.1 off end # PCI Express Port 10
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device pci 1d.2 off end # PCI Express Port 11
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device pci 1d.3 off end # PCI Express Port 12
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device pci 1e.0 off end # UART #0
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device pci 1e.1 off end # UART #1
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device pci 1e.2 off end # GSPI #0
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device pci 1e.3 off end # GSPI #1
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device pci 1f.0 on # LPC Interface
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device ref pcie_rp10 off end
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device ref pcie_rp11 off end
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device ref pcie_rp12 off end
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device ref uart0 off end
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device ref uart1 off end
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device ref gspi0 off end
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device ref gspi1 off end
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device ref lpc_espi on
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register "gen1_dec" = "0x000c0681"
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register "gen2_dec" = "0x000c1641"
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register "gen3_dec" = "0x00fc0201"
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@ -174,14 +174,14 @@ chip soc/intel/cannonlake
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device pnp 4e.19 off end # Power Management Channel 5
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end
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end
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device pci 1f.1 on end # P2SB
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device pci 1f.2 hidden end # Power Management Controller
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device pci 1f.3 on # Intel HDA
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device ref p2sb on end
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device ref pmc hidden end
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device ref hda on
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register "PchHdaAudioLinkHda" = "1"
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end
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device pci 1f.4 on end # SMBus
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device pci 1f.5 on end # PCH SPI
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device pci 1f.6 off end # GbE
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device ref smbus on end
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device ref fast_spi on end
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device ref gbe off end
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end
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chip drivers/crb
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device mmio 0xfed40000 on end
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