From 023968453e13f09420c8d6ecdeeb42a229c0ff09 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 5 Jun 2021 12:34:23 +0200 Subject: [PATCH] sb/intel/bd82x6x: Use array for PCIe ASPM overrides MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Using an array reduces the amount of boilerplate code. Change-Id: Ic6a48a01d3b96e69273dc28bdb6699ce7c0931b2 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/55246 Reviewed-by: Michael Niewöhner Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/mainboard/google/butterfly/devicetree.cb | 2 +- src/mainboard/google/stout/devicetree.cb | 2 +- src/southbridge/intel/bd82x6x/chip.h | 9 +------ src/southbridge/intel/bd82x6x/pcie.c | 27 +------------------- 4 files changed, 4 insertions(+), 36 deletions(-) diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index 9dee30f54d..725cbd1700 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -72,7 +72,7 @@ chip northbridge/intel/sandybridge device pci 1c.1 on end # PCIe Port #2 (ETH0) device pci 1c.2 on end # PCIe Port #3 (Card Reader) #force ASPM for PCIe bridge to Card Reader - register "pcie_aspm_f2" = "0x3" + register "pcie_aspm[2]" = "0x3" device pci 1c.3 off end # PCIe Port #4 device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 1ec596eda1..914ab601e0 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -76,7 +76,7 @@ chip northbridge/intel/sandybridge device pci 1c.0 on end # PCIe Port #1 device pci 1c.1 on end # PCIe Port #2 (WLAN) device pci 1c.2 on end # PCIe Port #3 (Card Reader) - register "pcie_aspm_f2" = "0x3" + register "pcie_aspm[2]" = "0x3" device pci 1c.3 off end # PCIe Port #4 device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 on end # PCIe Port #6 (LAN) diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 45f1226bdc..ac29944070 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -61,14 +61,7 @@ struct southbridge_intel_bd82x6x_config { uint8_t pcie_port_coalesce; /* Override PCIe ASPM */ - uint8_t pcie_aspm_f0; - uint8_t pcie_aspm_f1; - uint8_t pcie_aspm_f2; - uint8_t pcie_aspm_f3; - uint8_t pcie_aspm_f4; - uint8_t pcie_aspm_f5; - uint8_t pcie_aspm_f6; - uint8_t pcie_aspm_f7; + uint8_t pcie_aspm[8]; int c2_latency; int docking_supported; diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 8513390828..399c73aebc 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -162,32 +162,7 @@ static void pch_pcie_pm_late(struct device *dev) pci_or_config32(dev, 0xd4, 1 << 1); /* Check for a rootport ASPM override */ - switch (PCI_FUNC(dev->path.pci.devfn)) { - case 0: - apmc = config->pcie_aspm_f0; - break; - case 1: - apmc = config->pcie_aspm_f1; - break; - case 2: - apmc = config->pcie_aspm_f2; - break; - case 3: - apmc = config->pcie_aspm_f3; - break; - case 4: - apmc = config->pcie_aspm_f4; - break; - case 5: - apmc = config->pcie_aspm_f5; - break; - case 6: - apmc = config->pcie_aspm_f6; - break; - case 7: - apmc = config->pcie_aspm_f7; - break; - } + apmc = config->pcie_aspm[PCI_FUNC(dev->path.pci.devfn)]; /* Setup the override or get the real ASPM setting */ if (apmc) {