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soc/amd/common/block/i2c/i23c_pad_def.h: fix off by one in define 

I23C_PAD_CTRL_SLEW_N_SHIFT is 6 and not 7 which matches both with the
PPR #57243 revision 1.53 and with I23C_PAD_CTRL_SLEW_N_MASK which covers
both bits 6 and 7.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I622717bebaffe34b6df5e578b082dc10e2a98256
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63216
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2022-03-30 21:44:39 +02:00
parent d025ab3bc2
commit 02512eeb2e
1 changed files with 1 additions and 1 deletions
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src/soc/amd/common/block/i2c/i23c_pad_def.h
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@ -17,7 +17,7 @@
#define I23C_PAD_CTRL_RX_SEL_OFF (0 << I23C_PAD_CTRL_RX_SHIFT)
#define I23C_PAD_CTRL_RX_SEL_ON (3 << I23C_PAD_CTRL_RX_SHIFT)
#define I23C_PAD_CTRL_SLEW_N_MASK (BIT(6) | BIT(7))
#define I23C_PAD_CTRL_SLEW_N_SHIFT 7
#define I23C_PAD_CTRL_SLEW_N_SHIFT 6
#define I23C_PAD_CTRL_SLEW_N_DIS (0 << I23C_PAD_CTRL_SLEW_N_SHIFT)
#define I23C_PAD_CTRL_SLEW_N_FAST (3 << I23C_PAD_CTRL_SLEW_N_SHIFT)
#define I23C_PAD_CTRL_FALLSLEW_SEL_MASK (BIT(8) | BIT(9))