From 0251ecdd62e9ee8a1061f29e8fc307a4109505da Mon Sep 17 00:00:00 2001 From: Joey Peng Date: Tue, 18 Jan 2022 15:30:32 +0800 Subject: [PATCH] mb/google/brya/var/taniks: Run time probe for NVMe SSD and MMC Taniks will use two PCIE port signals with one slot, one CLK and one CLKREQ at next build. In order to accommodate this, probe statements are added to the devicetree. This only affects NVME SSD and EMMC. BUG=b:215040000 TEST=Build FSP with debug output enabled, and observe the correct root ports being initialized depending on the FW_CONFIG values for BOOT_EMMC and BOOT_NVME. Cq-Depend:chromium:3397561 Signed-off-by: Joey Peng Change-Id: I2ead505088f19fd3bf9768b541838395c82ef051 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61170 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Paul Menzel --- .../brya/variants/taniks/overridetree.cb | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/src/mainboard/google/brya/variants/taniks/overridetree.cb b/src/mainboard/google/brya/variants/taniks/overridetree.cb index ab98312628..96d4ad5ed7 100644 --- a/src/mainboard/google/brya/variants/taniks/overridetree.cb +++ b/src/mainboard/google/brya/variants/taniks/overridetree.cb @@ -223,6 +223,7 @@ chip soc/intel/alderlake .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + probe BOOT_NVME_MASK BOOT_NVME_ENABLED end device ref tbt_pcie_rp0 off end device ref tbt_pcie_rp1 off end @@ -345,6 +346,23 @@ chip soc/intel/alderlake end end end + device ref pcie_rp9 on + # Enable NVMe PCIE 9 using clk 0 + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "0" + device generic 0 on + probe BOOT_EMMC_MASK BOOT_EMMC_ENABLED + end + end + probe BOOT_EMMC_MASK BOOT_EMMC_ENABLED + end device ref pch_espi on chip ec/google/chromeec use conn0 as mux_conn[0]