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sc7180: enable RECOVERY_MRC_CACHE 

Enable caching of memory training data for recovery as well as normal
mode because memory training is taking too long in recovery as well.
This required creating a space in the fmap for RECOVERY_MRC_CACHE.

BUG=b:150502246
BRANCH=None
TEST=Run power_state:rec twice on lazor.  Ensure that on first boot,
     memory training occurs and on second boot, memory training is
     skipped.

Change-Id: Id9059a8edd7527b0fe6cdc0447920d5ecbdf296e
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46651
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Shelley Chen 2020-10-21 22:46:14 -07:00
parent 3827f56fe1
commit 0263e0ff65
3 changed files with 10 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/mainboard/google/trogdor/chromeos.fmd
View File

@ -14,7 +14,10 @@ FLASH@0x0 8M {
RW_VPD(PRESERVE) 32K
RW_NVRAM(PRESERVE) 16K
RW_MRC_CACHE(PRESERVE) 8K
UNIFIED_MRC_CACHE(PRESERVE) 16K {
RECOVERY_MRC_CACHE 8K
RW_MRC_CACHE 8K
}
RW_ELOG(PRESERVE) 4K
RW_SHARED 4K {
SHARED_DATA

26
src/soc/qualcomm/common/qclib.c
View File

@ -74,14 +74,6 @@ static void write_table_entry(struct qclib_cb_if_table_entry *te)
} else if (!strncmp(QCLIB_TE_DDR_TRAINING_DATA, te->name,
sizeof(te->name))) {
/*
* Don't store training data if we're in recovery mode
* because we always want to retrain due to
* possibility of RW training data possibly being
* updated to a different format.
*/
if (vboot_recovery_mode_enabled())
return;
assert(!mrc_cache_stash_data(MRC_TRAINING_DATA, QCLIB_VERSION,
(const void *)te->blob_address, te->size));
@ -138,20 +130,12 @@ void qclib_load_and_run(void)
/* output area, QCLib fills in DDR details */
qclib_add_if_table_entry(QCLIB_TE_DDR_INFORMATION, NULL, 0, 0);
/*
* We never want to use training data when booting into
* recovery mode.
*/
if (vboot_recovery_mode_enabled()) {
/* Attempt to load DDR Training Blob */
data_size = mrc_cache_load_current(MRC_TRAINING_DATA, QCLIB_VERSION,
_ddr_training, REGION_SIZE(ddr_training));
if (data_size < 0) {
printk(BIOS_ERR, "Unable to load previous training data.\n");
memset(_ddr_training, 0, REGION_SIZE(ddr_training));
} else {
/* Attempt to load DDR Training Blob */
data_size = mrc_cache_load_current(MRC_TRAINING_DATA, QCLIB_VERSION,
_ddr_training, REGION_SIZE(ddr_training));
if (data_size < 0) {
printk(BIOS_ERR, "Unable to load previous training data.\n");
memset(_ddr_training, 0, REGION_SIZE(ddr_training));
}
}
qclib_add_if_table_entry(QCLIB_TE_DDR_TRAINING_DATA,
_ddr_training, REGION_SIZE(ddr_training), 0);

1
src/soc/qualcomm/sc7180/Kconfig
View File

@ -19,6 +19,7 @@ config SOC_QUALCOMM_SC7180
select MAINBOARD_FORCE_NATIVE_VGA_INIT
select HAVE_LINEAR_FRAMEBUFFER
select CACHE_MRC_SETTINGS
select HAS_RECOVERY_MRC_CACHE
select COMPRESS_BOOTBLOCK
if SOC_QUALCOMM_SC7180