soc/intel/xeon-sp,mb/ocp/tiogapass: Don't fake binaries
If we don't pretend to have binaries, there is no need to add fake ones. This also fixes building the default config. Change-Id: I8f933f24a734a9ce3d82ef57f7f234ee4dfa86e9 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39383 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -56,7 +56,7 @@ config FSP_USE_REPO
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depends on SOC_INTEL_APOLLOLAKE || SOC_INTEL_SKYLAKE || \
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SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE || \
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SOC_INTEL_ICELAKE || SOC_INTEL_WHISKEYLAKE || \
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SOC_INTEL_DENVERTON_NS || SOC_INTEL_XEON_SP
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SOC_INTEL_DENVERTON_NS
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help
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When selecting this option, the SoC must set FSP_HEADER_PATH
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and FSP_FD_PATH correctly so FSP splitting works.
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@ -19,7 +19,6 @@ if BOARD_OCP_TIOGAPASS
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select ADD_FSP_BINARIES
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select BOARD_ROMSIZE_KB_32768
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select HAVE_ACPI_TABLES
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select SOC_INTEL_XEON_SP
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@ -37,7 +37,6 @@ config CPU_SPECIFIC_OPTIONS
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select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS
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select FSP_T_XIP
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select FSP_M_XIP
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select FSP_USE_REPO
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select POSTCAR_STAGE
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select IOAPIC
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select PARALLEL_MP
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@ -55,6 +54,7 @@ config CPU_SPECIFIC_OPTIONS
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select TSC_MONOTONIC_TIMER
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select UDELAY_TSC
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select SUPPORT_CPU_UCODE_IN_CBFS
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select MICROCODE_BLOB_NOT_HOOKED_UP
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select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
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config MAINBOARD_USES_FSP2_0
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@ -69,14 +69,6 @@ config USE_FSP2_0_DRIVER
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select POSTCAR_CONSOLE
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select POSTCAR_STAGE
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# Fake FSP binary is used, as the current FSP binary for SKX-SP
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# is an engineering build. It is not available to the public
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# for now.
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config FSP_FD_PATH
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string "Location of FSP binary"
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depends on FSP_USE_REPO
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default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd"
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config FSP_HEADER_PATH
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string "Location of FSP headers"
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depends on MAINBOARD_USES_FSP2_0
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