GNUBoot/coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

soc/amd/common/block/lpc/lpc: increase size of SPI BAR to 4kByte

Browse source 
The memory map granularity for those devices is 4kByte.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8806128bdce8988f5cd7c8fa8a342fdb01eb7f42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Felix Held 2023-04-29 01:59:31 +02:00 committed by Matt DeVillier
parent 662d7af70b
commit 026caf5def
1 changed files with 1 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/soc/amd/common/block/lpc/lpc.c
View file

@ -121,7 +121,7 @@ static void lpc_read_resources(struct device *dev)
FLASH_BELOW_4GB_MAPPING_REGION_SIZE);
/* Add a memory resource for the SPI BAR. */
mmio_range(dev, 2, SPI_BASE_ADDRESS, 1 * KiB);
mmio_range(dev, 2, SPI_BASE_ADDRESS, 4 * KiB);
res = new_resource(dev, 3); /* IOAPIC */
res->base = IO_APIC_ADDR;