mb/lenovo/t520: Switch to overridetree
Change-Id: If6be9cffe97dcd8f733e3bd5a67a408dd817005a Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37295 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Peter Lemenkov
Patrick Georgi
parent
99035650aa
commit
02b29b9d01
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@ -51,9 +51,9 @@ config MAINBOARD_DIR
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string
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default "lenovo/t520"
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config DEVICETREE
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config OVERRIDE_DEVICETREE
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string
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default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
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default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
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config FMDFILE
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string
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@ -90,7 +90,7 @@ chip northbridge/intel/sandybridge
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end # PCIe Port #4 Express Card
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device pci 1c.4 on end # PCIe Port #5 MMC/SDXC + IEEE1394
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device pci 1c.5 off end # PCIe Port #6 Intel Ethernet PHY
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device pci 1c.6 on end # PCIe Port #7 USB 3.0 only W520
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device pci 1c.6 off end # PCIe Port #7
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device pci 1c.7 off end # PCIe Port #8
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device pci 1d.0 on end # USB2 EHCI #1
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@ -1,180 +0,0 @@
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chip northbridge/intel/sandybridge
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# IGD Displays
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register "gfx.ndid" = "3"
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register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
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# Enable DisplayPort Hotplug with 6ms pulse
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register "gpu_dp_d_hotplug" = "0x06"
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# Enable Panel as LVDS and configure power delays
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register "gpu_panel_port_select" = "0" # LVDS
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register "gpu_panel_power_cycle_delay" = "5"
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register "gpu_panel_power_up_delay" = "300" # T1+T2: 30ms
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register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms
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register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms
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register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms
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register "gfx.use_spread_spectrum_clock" = "1"
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register "gfx.link_frequency_270_mhz" = "1"
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register "gpu_cpu_backlight" = "0x1155"
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register "gpu_pch_backlight" = "0x06100610"
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device cpu_cluster 0 on
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chip cpu/intel/model_206ax
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# Magic APIC ID to locate this chip
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device lapic 0x0 on end
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device lapic 0xacac off end
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register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1)
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register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
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register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)
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register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1)
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register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
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register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)
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end
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end
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register "pci_mmio_size" = "2048"
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device domain 0 on
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subsystemid 0x17aa 0x21cf inherit
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device pci 00.0 on end # host bridge
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device pci 01.0 on end # NVIDIA Corporation GF119M [NVS 4200M]
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device pci 02.0 on
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subsystemid 0x17aa 0x21d1
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end # vga controller
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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# GPI routing
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# 0 No effect (default)
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# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
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# 2 SCI (if corresponding GPIO_EN bit is also set)
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register "alt_gp_smi_en" = "0x0000"
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register "gpi1_routing" = "2"
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register "gpi13_routing" = "2"
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# Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 3 (eSATA) & 4 (dock)
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register "sata_port_map" = "0x1f"
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# Set max SATA speed to 6.0 Gb/s
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register "sata_interface_speed_support" = "0x3"
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register "gen1_dec" = "0x7c1601"
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register "gen2_dec" = "0x0c15e1"
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register "gen4_dec" = "0x0c06a1"
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# Enable zero-based linear PCIe root port functions
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register "pcie_port_coalesce" = "1"
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register "c2_latency" = "101" # c2 not supported
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register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
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register "spi_uvscc" = "0x2005"
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register "spi_lvscc" = "0x2005"
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end
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device pci 16.2 off end
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device pci 16.3 off end
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device pci 19.0 on # Intel Gigabit Ethernet
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subsystemid 0x17aa 0x21ce
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end
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device pci 1a.0 on end # USB2 EHCI #2
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device pci 1b.0 on end # High Definition Audio
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device pci 1c.0 off end # PCIe Port #1
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device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN
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device pci 1c.2 off end # PCIe Port #3
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device pci 1c.3 on
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smbios_slot_desc "7" "3" "ExpressCard Slot" "8"
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end # PCIe Port #4 Express Card
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device pci 1c.4 on end # PCIe Port #5 MMC/SDXC + IEEE1394
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device pci 1c.5 off end # PCIe Port #6 Intel Ethernet PHY
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device pci 1c.6 off end # PCIe Port #7 USB 3.0 only W520
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device pci 1c.7 off end # PCIe Port #8
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device pci 1d.0 on end # USB2 EHCI #1
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device pci 1e.0 off end # PCI-2-PCI bridge
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device pci 1f.0 on #LPC bridge
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chip ec/lenovo/pmh7
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device pnp ff.1 on end # dummy
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register "backlight_enable" = "0x01"
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register "dock_event_enable" = "0x01"
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end
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chip drivers/pc80/tpm
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device pnp 0c31.0 on end
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end
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chip ec/lenovo/h8
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device pnp ff.2 on # dummy
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io 0x60 = 0x62
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io 0x62 = 0x66
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io 0x64 = 0x1600
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io 0x66 = 0x1604
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end
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register "config0" = "0xa7"
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register "config1" = "0x09"
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register "config2" = "0xa0"
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register "config3" = "0xc2"
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register "beepmask0" = "0x00"
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register "beepmask1" = "0x86"
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register "has_power_management_beeps" = "0"
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register "event2_enable" = "0xff"
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register "event3_enable" = "0xff"
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register "event4_enable" = "0xd0"
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register "event5_enable" = "0xfc"
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register "event6_enable" = "0x00"
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register "event7_enable" = "0x01"
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register "event8_enable" = "0x7b"
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register "event9_enable" = "0xff"
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register "eventa_enable" = "0x01"
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register "eventb_enable" = "0x00"
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register "eventc_enable" = "0xff"
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register "eventd_enable" = "0xff"
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register "evente_enable" = "0x0d"
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register "has_bdc_detection" = "1"
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register "bdc_gpio_num" = "54"
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register "bdc_gpio_lvl" = "0"
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register "has_wwan_detection" = "1"
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register "wwan_gpio_num" = "70"
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register "wwan_gpio_lvl" = "0"
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end
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chip drivers/lenovo/hybrid_graphics
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device pnp ff.f on end # dummy
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register "detect_gpio" = "21"
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register "has_panel_hybrid_gpio" = "1"
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register "panel_hybrid_gpio" = "52"
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register "panel_integrated_lvl" = "1"
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register "has_backlight_gpio" = "0"
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register "has_dgpu_power_gpio" = "0"
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register "has_thinker1" = "1"
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end
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end # LPC bridge
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device pci 1f.2 on end # SATA Controller 1
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device pci 1f.3 on # SMBUS controller
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# eeprom, 8 virtual devices, same chip
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chip drivers/i2c/at24rf08c
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device i2c 54 on end
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device i2c 55 on end
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device i2c 56 on end
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device i2c 57 on end
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device i2c 5c on end
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device i2c 5d on end
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device i2c 5e on end
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device i2c 5f on end
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end
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end # SMBus
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device pci 1f.5 off end # IDE controller
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device pci 1f.6 off end # Thermal controller
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end
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end
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end
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@ -0,0 +1,16 @@
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chip northbridge/intel/sandybridge
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device domain 0 on
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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device pci 1e.0 off end # PCI-2-PCI bridge
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device pci 1f.0 on # LPC bridge
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chip ec/lenovo/h8
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register "has_wwan_detection" = "1"
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register "wwan_gpio_num" = "70"
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register "wwan_gpio_lvl" = "0"
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end
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end # LPC bridge
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device pci 1f.5 off end # IDE controller
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device pci 1f.6 off end # Thermal controller
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end
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end
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end
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@ -0,0 +1,7 @@
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chip northbridge/intel/sandybridge
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device domain 0 on
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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device pci 1c.6 on end # PCIe Port #7 USB 3.0
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end
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end
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end
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