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mb/msi/ms7d25: Add correct memory init configuration 

Tested with 4x KINGSTON KF3600C17D4/8GX DIMMs.

TEST=Include the microcode from vendor firmware and FSP blob from
Intel R&DC. Boot the platform and see ramstage is executing.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I98b9c77d791d18640cb05c133cb0bf14ad22dcdb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
This commit is contained in:
Michał Żygowski 2022-04-08 17:12:13 +02:00 committed by Felix Held
parent bb1a0e82d7
commit 02db6b4049
1 changed files with 3 additions and 8 deletions
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11
src/mainboard/msi/ms7d25/romstage_fsp_params.c
View File

@ -9,18 +9,13 @@
static const struct mb_cfg ddr4_mem_config = { static const struct mb_cfg ddr4_mem_config = {
.type = MEM_TYPE_DDR4, .type = MEM_TYPE_DDR4,
.rcomp = { /* According to DOC #573387 rcomp values no longer have to be provided */
/* Baseboard uses only 100ohm Rcomp resistor FIXME */ /* DDR DIMM configuration does not need to set DQ/DQS maps */
.resistor = 100,
/* Baseboard Rcomp target values FIXME */
.targets = { 50, 20, 25, 25, 25 },
},
.UserBd = BOARD_TYPE_DESKTOP_2DPC, /* FIXME */ .UserBd = BOARD_TYPE_DESKTOP_2DPC, /* FIXME */
.ddr_config = { .ddr_config = {
.dq_pins_interleaved = false, /* FIXME */ .dq_pins_interleaved = true,
}, },
}; };