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usbdebug: Fixes for LynxPoint LP 

Keep the EHCI BAR unchanged to keep usbdebug working.

Change-Id: I7fe0eed24a66cb5058b49ee3fc0350d91089ed7a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3477
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This commit is contained in:
Kyösti Mälkki 2013-08-13 09:10:31 +03:00
parent 690bf2f333
commit 0306b50280
2 changed files with 12 additions and 4 deletions
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4
src/southbridge/intel/lynxpoint/Kconfig
View File

@ -27,7 +27,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select SOUTHBRIDGE_INTEL_COMMON
select IOAPIC
select HAVE_HARD_RESET
select HAVE_USBDEBUG
select HAVE_USBDEBUG_OPTIONS
select USE_WATCHDOG_ON_BOOT
select PCIEXP_ASPM
select PCIEXP_COMMON_CLOCK
@ -42,7 +42,7 @@ config INTEL_LYNXPOINT_LP
config EHCI_BAR
hex
default 0xfef00000
default 0xe8000000
config EHCI_DEBUG_OFFSET
hex

12
src/southbridge/intel/lynxpoint/early_usb.c
View File

@ -24,8 +24,16 @@
#include <device/pci_def.h>
#include "pch.h"
#define PCH_EHCI1_TEMP_BAR0 0xe8000000
#define PCH_EHCI2_TEMP_BAR0 0xe8000400
/* HCD_INDEX==2 selects 0:1a.0 (PCH_EHCI2), any other index
* selects 0:1d.0 (PCH_EHCI1) for usbdebug use.
*/
#if CONFIG_USBDEBUG_HCD_INDEX != 2
#define PCH_EHCI1_TEMP_BAR0 CONFIG_EHCI_BAR
#define PCH_EHCI2_TEMP_BAR0 (PCH_EHCI1_TEMP_BAR0 + 0x400)
#else
#define PCH_EHCI2_TEMP_BAR0 CONFIG_EHCI_BAR
#define PCH_EHCI1_TEMP_BAR0 (PCH_EHCI2_TEMP_BAR0 + 0x400)
#endif
/*
* Setup USB controller MMIO BAR to prevent the