From 0318dc169ec256108dcffd273efc5b83b3a54a58 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Fri, 21 May 2021 16:31:52 -0600 Subject: [PATCH] soc/amd/common/block/espi: Increase ESPI_CH_READY_TIMEOUT_US to 10ms The ChromeEC might take longer than 1ms for the peripheral channel to be enabled. The PLTRST# interrupt handler takes about ~539us. This doesn't account for the time it takes for the interrupt handler to be scheduled. Increasing the timeout to 10ms gives ample time. BUG=b:188188172, b:188935533 TEST=Boot guybrush and no longer see channel enable errors Suggested-by: Rob Barnes Signed-off-by: Raul E Rangel Change-Id: Ib6db577bf06175ceb17b446af706ad8c9f891481 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54788 Reviewed-by: Jason Glenesk Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/lpc/espi_util.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index 9bad4c2152..0ea014fee2 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -371,7 +371,7 @@ enum espi_cmd_type { #define ESPI_RXVW_POLARITY 0xac #define ESPI_CMD_TIMEOUT_US 100 -#define ESPI_CH_READY_TIMEOUT_US 1000 +#define ESPI_CH_READY_TIMEOUT_US 10000 union espi_txhdr0 { uint32_t val;