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google/fizz: Configure memory 

Read DRAM SPD and populate MemorySpdPtr fields
in UPD data structure for FSP.

BUG=b:36490168, b:35775024
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/fizz -x -a
     We are currently working on bringup and have no
     hardware to test on yet.

Change-Id: I191cc6bf1fd8aa461855c538b48fd39e3ffd7848
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/19205
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Shelley Chen 2017-04-07 09:15:42 -07:00 committed by Martin Roth
parent b7f28700f4
commit 031c818633
2 changed files with 20 additions and 0 deletions
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9
src/mainboard/google/fizz/Kconfig
View File

@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS
select MAINBOARD_USES_FSP2_0
select NO_FADT_8042
select SOC_INTEL_KABYLAKE
select GENERIC_SPD_BIN
config VBOOT
select EC_GOOGLE_CHROMEEC_SWITCHES
@ -38,4 +39,12 @@ config MAINBOARD_FAMILY
config MAX_CPUS
int
default 8
config DIMM_MAX
int
default 2
config DIMM_SPD_SIZE
int
default 512
endif

11
src/mainboard/google/fizz/romstage.c
View File

@ -15,6 +15,7 @@
#include <soc/romstage.h>
#include <string.h>
#include <spd_bin.h>
#include <fsp/soc_binding.h>
@ -28,4 +29,14 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
memcpy(&mem_cfg->RcompResistor, rcomp_resistor, sizeof(rcomp_resistor));
memcpy(&mem_cfg->RcompTarget, rcomp_target, sizeof(rcomp_target));
/* Read spd block to get memory config */
struct spd_block blk;
mem_cfg->DqPinsInterleaved = 1;
get_spd_smbus(&blk);
mem_cfg->MemorySpdDataLen = blk.len;
mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];
mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1];
dump_spd_info(&blk);
}