sb/intel/lynxpoint: Use unions for ME PCI registers
Wrap bitfield structs in unions to reduce pointer usage. Change-Id: I8ac901211beb0ef24dff926b1a06004a99e68bda Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Angel Pons
Felix Held
parent
9f043742a8
commit
032255c90f
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@ -20,26 +20,10 @@ static const char *me_ack_values[] = {
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[ME_HFS_ACK_CONTINUE] = "Continue to boot"
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};
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static inline void pci_read_dword_ptr(void *ptr, int offset)
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{
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u32 dword = pci_read_config32(PCH_ME_DEV, offset);
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memcpy(ptr, &dword, sizeof(dword));
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}
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static inline void pci_write_dword_ptr(void *ptr, int offset)
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{
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u32 dword = 0;
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memcpy(&dword, ptr, sizeof(dword));
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pci_write_config32(PCH_ME_DEV, offset, dword);
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}
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void intel_early_me_status(void)
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{
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struct me_hfs hfs;
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struct me_hfs2 hfs2;
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pci_read_dword_ptr(&hfs, PCI_ME_HFS);
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pci_read_dword_ptr(&hfs2, PCI_ME_HFS2);
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union me_hfs hfs = { .raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS) };
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union me_hfs2 hfs2 = { .raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS2) };
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intel_me_status(&hfs, &hfs2);
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}
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@ -47,15 +31,15 @@ void intel_early_me_status(void)
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int intel_early_me_init(void)
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{
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int count;
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struct me_uma uma;
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struct me_hfs hfs;
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union me_uma uma;
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union me_hfs hfs;
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printk(BIOS_INFO, "Intel ME early init\n");
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/* Wait for ME UMA SIZE VALID bit to be set */
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/* FIXME: ME9 BGW indicates a 5 sec poll timeout. */
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for (count = ME_RETRY; count > 0; --count) {
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pci_read_dword_ptr(&uma, PCI_ME_UMA);
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uma.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_UMA);
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if (uma.valid)
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break;
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udelay(ME_DELAY);
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@ -66,7 +50,7 @@ int intel_early_me_init(void)
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}
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/* Check for valid firmware */
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pci_read_dword_ptr(&hfs, PCI_ME_HFS);
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hfs.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS);
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if (hfs.fpt_bad) {
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printk(BIOS_WARNING, "WARNING: ME has bad firmware\n");
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return -1;
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@ -78,9 +62,8 @@ int intel_early_me_init(void)
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int intel_early_me_uma_size(void)
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{
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struct me_uma uma;
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union me_uma uma = { .raw = pci_read_config32(PCH_ME_DEV, PCI_ME_UMA) };
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pci_read_dword_ptr(&uma, PCI_ME_UMA);
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if (uma.valid) {
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printk(BIOS_DEBUG, "ME: Requested %uMB UMA\n", uma.size);
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return uma.size;
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@ -108,8 +91,8 @@ int intel_early_me_init_done(u8 status)
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u8 reset;
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int count;
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u32 mebase_l, mebase_h;
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struct me_hfs hfs;
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struct me_did did = {
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union me_hfs hfs;
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union me_did did = {
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.init_done = ME_INIT_DONE,
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.status = status
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};
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@ -123,7 +106,7 @@ int intel_early_me_init_done(u8 status)
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printk(BIOS_DEBUG, "ME: Sending Init Done with status: %d, "
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"UMA base: 0x%04x\n", status, did.uma_base);
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pci_write_dword_ptr(&did, PCI_ME_H_GS);
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pci_write_config32(PCH_ME_DEV, PCI_ME_H_GS, did.raw);
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/*
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* The ME firmware does not respond with an ACK when NOMEM or ERROR
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@ -134,7 +117,7 @@ int intel_early_me_init_done(u8 status)
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/* Must wait for ME acknowledgement */
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for (count = ME_RETRY; count > 0; --count) {
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pci_read_dword_ptr(&hfs, PCI_ME_HFS);
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hfs.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS);
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if (hfs.bios_msg_ack)
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break;
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udelay(ME_DELAY);
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@ -92,13 +92,6 @@ static inline void mei_write_dword_ptr(void *ptr, int offset)
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mei_dump(ptr, dword, offset, "WRITE");
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}
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static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset)
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{
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u32 dword = pci_read_config32(dev, offset);
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memcpy(ptr, &dword, sizeof(dword));
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mei_dump(ptr, dword, offset, "PCI READ");
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}
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static inline void read_host_csr(struct mei_csr *csr)
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{
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mei_read_dword_ptr(csr, MEI_H_CSR);
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@ -434,11 +427,11 @@ static void intel_me_mbp_give_up(struct device *dev)
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static void intel_me_mbp_clear(struct device *dev)
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{
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int count;
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struct me_hfs2 hfs2;
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union me_hfs2 hfs2;
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/* Wait for the mbp_cleared indicator */
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for (count = ME_RETRY; count > 0; --count) {
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pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2);
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hfs2.raw = pci_read_config32(dev, PCI_ME_HFS2);
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if (hfs2.mbp_cleared)
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break;
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udelay(ME_DELAY);
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@ -539,7 +532,7 @@ static int mkhi_end_of_post(void)
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void intel_me_finalize(struct device *dev)
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{
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struct me_hfs hfs;
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union me_hfs hfs;
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u32 reg32;
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reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
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@ -553,8 +546,7 @@ void intel_me_finalize(struct device *dev)
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intel_me_mbp_clear(dev);
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/* Make sure ME is in a mode that expects EOP */
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reg32 = pci_read_config32(dev, PCI_ME_HFS);
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memcpy(&hfs, ®32, sizeof(u32));
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hfs.raw = pci_read_config32(dev, PCI_ME_HFS);
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/* Abort and leave device alone if not normal mode */
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if (hfs.fpt_bad ||
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@ -599,11 +591,8 @@ static int me_icc_set_clock_enables(u32 mask)
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static enum me_bios_path intel_me_path(struct device *dev)
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{
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enum me_bios_path path = ME_DISABLE_BIOS_PATH;
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struct me_hfs hfs;
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struct me_hfs2 hfs2;
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pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS);
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pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2);
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union me_hfs hfs = { .raw = pci_read_config32(dev, PCI_ME_HFS) };
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union me_hfs2 hfs2 = { .raw = pci_read_config32(dev, PCI_ME_HFS2) };
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/* Check and dump status */
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intel_me_status(&hfs, &hfs2);
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@ -693,11 +682,10 @@ static int intel_mei_setup(struct device *dev)
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/* Read the Extend register hash of ME firmware */
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static int intel_me_extend_valid(struct device *dev)
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{
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struct me_heres status;
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union me_heres status = { .raw = pci_read_config32(dev, PCI_ME_HERES) };
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u32 extend[8] = {0};
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int i, count = 0;
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pci_read_dword_ptr(dev, &status, PCI_ME_HERES);
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if (!status.extend_feature_present) {
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printk(BIOS_ERR, "ME: Extend Feature not present\n");
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return -1;
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@ -762,12 +750,10 @@ static int intel_me_read_mbp(struct me_bios_payload *mbp_data, struct device *de
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struct mbp_header mbp_hdr;
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u32 me2host_pending;
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struct mei_csr host;
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struct me_hfs2 hfs2;
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union me_hfs2 hfs2 = { .raw = pci_read_config32(dev, PCI_ME_HFS2) };
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struct mbp_payload *mbp;
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int i;
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pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2);
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if (!hfs2.mbp_rdy) {
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printk(BIOS_ERR, "ME: MBP not ready\n");
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goto mbp_failure;
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@ -50,7 +50,8 @@
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#define ME_HFS_ACK_GBL_RESET 6
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#define ME_HFS_ACK_CONTINUE 7
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struct me_hfs {
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union me_hfs {
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struct __packed {
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u32 working_state: 4;
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u32 mfg_mode: 1;
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u32 fpt_bad: 1;
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@ -64,17 +65,22 @@ struct me_hfs {
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u32 boot_options_present: 1;
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u32 ack_data: 3;
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u32 bios_msg_ack: 4;
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} __packed;
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};
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u32 raw;
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};
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#define PCI_ME_UMA 0x44
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struct me_uma {
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union me_uma {
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struct __packed {
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u32 size: 6;
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u32 reserved_1: 10;
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u32 valid: 1;
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u32 reserved_0: 14;
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u32 set_to_one: 1;
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} __packed;
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};
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u32 raw;
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};
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#define PCI_ME_H_GS 0x4c
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#define ME_INIT_DONE 1
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@ -83,13 +89,16 @@ struct me_uma {
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#define ME_INIT_STATUS_ERROR 2
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#define ME_INIT_STATUS_SUCCESS_OTHER 3 /* SEE ME9 BWG */
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struct me_did {
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union me_did {
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struct __packed {
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u32 uma_base: 16;
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u32 reserved: 7;
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u32 rapid_start: 1;
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u32 status: 4;
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u32 init_done: 4;
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} __packed;
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};
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u32 raw;
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};
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/*
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* Apparently the GMES register is renamed to HFS2 (or HFSTS2 according
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@ -165,7 +174,8 @@ struct me_did {
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#define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF 0xb
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#define ME_HFS2_PMEVENT_SXMX_SXMOFF 0xc
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struct me_hfs2 {
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union me_hfs2 {
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struct __packed {
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u32 bist_in_progress: 1;
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u32 reserved1: 2;
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u32 invoke_mebx: 1;
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@ -180,7 +190,9 @@ struct me_hfs2 {
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u32 current_state: 8;
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u32 current_pmevent: 4;
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u32 progress_code: 4;
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} __packed;
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};
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u32 raw;
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};
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#define PCI_ME_H_GS2 0x70
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#define PCI_ME_MBP_GIVE_UP 0x01
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@ -190,12 +202,15 @@ struct me_hfs2 {
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#define PCI_ME_EXT_SHA256 0x02
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#define PCI_ME_HER(x) (0xc0+(4*(x)))
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struct me_heres {
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union me_heres {
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struct __packed {
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u32 extend_reg_algorithm: 4;
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u32 reserved: 26;
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u32 extend_feature_present: 1;
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u32 extend_reg_valid: 1;
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} __packed;
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};
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u32 raw;
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};
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/*
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* Management Engine MEI registers
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@ -313,7 +328,7 @@ enum me_bios_path {
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};
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/* Defined in me_status.c for both romstage and ramstage */
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void intel_me_status(struct me_hfs *hfs, struct me_hfs2 *hfs2);
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void intel_me_status(union me_hfs *hfs, union me_hfs2 *hfs2);
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void intel_early_me_status(void);
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int intel_early_me_init(void);
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@ -123,7 +123,7 @@ static const char *me_progress_policy_values[] = {
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[ME_HFS2_STATE_POLICY_VSCC_NO_MATCH] = "Required VSCC values for flash parts do not match",
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};
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void intel_me_status(struct me_hfs *hfs, struct me_hfs2 *hfs2)
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void intel_me_status(union me_hfs *hfs, union me_hfs2 *hfs2)
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{
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if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL < BIOS_DEBUG)
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return;
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